Intel Corporation

Intel Mobile Communications Gmbh

Kailash Chandrashekar

Ashoke Ravi

Stefano Pellerano

Paolo Madoglio

Stephan Henzler

Georgios Yorgos Palaskas

Markus Schimper

Alon Cohen

William Li

Oren Shalita

Sharon Heruti

Hyung Seok Kim

Natarajan Karthik

Roy Sofer

An EC platform including a controller to control multiple integrated circuits (ICs) to synchronize an operational internal clock signal of an IC with a master clock signal. The controller generates commands for the IC to measure a phase difference or latency difference between an initial internal clock signal of the IC and an input clock signal to the IC from a parent IC. The controller further receives a difference signal from the IC to indicate the phase or latency difference. The IC includes a measurement circuit to measure the phase or latency difference, and to generate a difference signal to indicate the phase or latency difference. The IC further includes a synchronization clock generator to generate, based on the initial internal clock signal and the difference signal, an operational internal clock signal synchronized with the master clock signal. Other embodiments may also be described and claimed.

Multi-chip synchronization with applications in multiple-input multiple-output (MIMO) radar systems

Methods, apparatus, systems and articles of manufacture for wideband and fast chirp generation for radar systems are disclosed herein. An example apparatus includes a phase digital-to-analog converter to convert a digital input that specifies at least one of a phase modulation or a frequency modulation into an analog output, and to generate a phase modulated output centered on an intermediate frequency. The example apparatus also includes a frequency multiplier to frequency multiply the phase modulated output centered on the intermediate frequency by a multiplication factor to generate a chirp signal.

Methods and apparatus for wideband and fast chirp generation for radar systems

This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information.

Segmented digital-to-time converter calibration

A re-circulating time-to-digital converter (TDC) can include a triggered reference ring oscillator (TRRO) and a delay module. The triggered reference ring oscillator can, when triggered by a reference signal edge, generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The delay module can store, in a plurality of latches, samples of a VCO signal docked by the periodic ring oscillator signal. Each latch can generate an output of the sample, and each latch output can represent a time difference polarity between VCO signal and TRRO signal. In another example, the re-circulating TDC can include the triggered reference ring oscillator, a digital frequency lock module, and a TDC post-process module. The digital frequency lock module can generate a ring oscillator control signal, which sets the ring oscillator period for the triggered reference ring oscillator. The TDC post-process module can generate a TDC output, which can be a binary representation of a phase difference between a reference signal and a VCO signal.

Re-circulating time-to-digital converter (TDC)

Representative implementations of devices and techniques provide a time delay based on an input value. A digital delay may be generated based on a coarse delay and a fine delay. The coarse delay may be selected based on the input value. The fine delay may be selected from an overlapping set of fine delay intervals, based on the selected coarse delay. In some implementations, a control component may be used to select the fine delay when more than one fine delay interval is indicated.

Redundant delay digital-to-time converter

A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.

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Hillsboro, OR, United States of America

Kailash Chandrashekar