Novellus Systems Incorporated

Lam Research Corporation

Kaihan Abidi Ashtiani

Karl B Levy

Joshua Collins

Bart Jan Van Schravendijk

Raashina Humayun

Kwok Fai Lai

Lana Hiului Chan

Juwen Gao

Larry D Hartsough

Michal Danek

Artur Kolics

Patrick A Van Cleemput

Nerissa Sue Draeger

Derek Wong

Junghwan Sung

Andrew L Nordquist

Yezdi N Dordi

Larry Zhao

Praveen Nalla

Maximilian Albert Biberger

William T Lee

Anand Chandrashekar

Erich R Klawuhn

Sanjay Gopinath

Feng Chen

James A Fair

Panya Wongsenakhum

Aaron R Fellis

Jason Daejin Park

Wei Tang

Xinye Liu

Karena Shannon

Mirko Glass

Anil Mane

J Patrick Rymer

Deenesh Padhi

John Stephen Drewery

Girish Anant Dixit

David Cohen

George Andrew Antonelli

Lawrence Schloss

Ronald Allan Powell

Shambhu Nath Roy

Sang-Hyeob Lee

Dhritiman Subha Kashyap

Gary B Lind

Chiukin Steven Lai

Richard S Hill

Vincent Burkhart

Michael J Wood

Jeong-Seok Na

Kapil Umesh Sawlani

Kevin Madrigal

Lakshminarayana Nittala

Michael Rumer

Robert Martinson

Jean Qing Lu

Natan Solomon

Lie Zhao

Gerard Chris D'Couto

George Tkach

Naohiro Shoda

Michael Danek

Hsiang-yun Lee

Jason Stevens

Frances Katherine Zelaya

Shu Tsai Wang

Anna Battaglia

Stefano Rassiga

Max Biberger

Jeff Dewayne Lyons

Disclosed are methods of depositing a transition metal such as tungsten on a semiconductor substrate. The method includes providing a gas mixture of diborane with a balance of hydrogen, where the hydrogen serves to stabilize the diborane in the gas mixture. The method further includes delivering the gas mixture to the semiconductor substrate to form a boron layer, where the boron layer serves as a reducing agent layer to convert a metal-containing precursor to metal, such as a tungsten-containing precursor to tungsten. In some implementations, the semiconductor substrate includes a vertical structure, such as a three-dimensional vertical NAND structure, with horizontal features or wordlines having openings in sidewalls of the vertical structure, where the boron layer may be conformally deposited in the horizontal features of the vertical structure.

Metal fill process for three-dimensional vertical NAND wordline

Provided herein are methods of filling gaps using high density plasma chemical vapor deposition (HDP CVD). According to various implementations, carbon-containing films such as amorphous carbon and amorphous carbide films are deposited by HDP CVD into gaps on substrates to fill the gaps. The methods may involve using high hydrogen-content process gasses during HDP CVD deposition to provide bottom-up fill. Also provided are related apparatus.

Gap fill using carbon-based films

A system includes a camera mounted external to and adjacent to a window of a processing chamber configured to process semiconductor substrates. The window allows the camera to view a component in the processing chamber. The camera is configured to generate a video signal indicative of a status of the component during a process being performed in the processing chamber. The system further includes a controller coupled to the processing chamber. The controller is configured to control the camera, process the video signal from the camera, determine the status of the component based on the processing of the video signal, and determine whether to terminate the process based on the status of the component.

In-situ chamber clean end point detection systems and methods using computer vision systems

Provided herein are methods of forming conductive cobalt (Co) interconnects and Co features. The methods involve deposition of a thin manganese (Mn)-containing film on a dielectric followed by subsequent deposition of cobalt on the Mn-containing film. The Mn-containing film may be deposited on a silicon-containing dielectric, such as silicon dioxide, and annealed to form a manganese silicate.

Manganese barrier and adhesion layers for cobalt

A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

Interlevel conductor pre-fill utilizing selective barrier deposition

Implementations of the methods and apparatus disclosed herein relate to pore sealing of porous dielectric films using flowable dielectric material. The methods involve exposing a substrate having an exposed porous dielectric film thereon to a vapor phase dielectric precursor under conditions such that a flowable dielectric material selectively deposits in the pores of the porous dielectric material. The pores can be filled with the deposited flowable dielectric material without depositing a continuous film on any exposed metal surface.

Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor

A dual-plenum showerhead for semiconductor processing operations is provided. The showerhead may include a faceplate with two sets of gas distribution holes, each set fed by a separate plenum. One set of gas distribution holes may be through-holes in the faceplate of the showerhead and may allow gases trapped between the faceplate and a plasma dome to flow towards a wafer. The other set of gas distribution holes may distribute gas routed through passages or channels in the faceplate towards the wafer. The passages or channels in the faceplate may include radial channels and annular channels and may be fed from an annular gas distribution channel about the periphery of the faceplate.

Dual plenum, axi-symmetric showerhead with edge-to-center gas delivery

A method for filling a trench in a substrate includes partially filling the trench with a first silicon dioxide layer. An amorphous silicon layer is deposited on the silicon dioxide layer. The trench is filled with a second silicon dioxide layer. An oxidation treatment is performed on the substrate to oxidize the amorphous silicon layer.

Systems and methods for eliminating seams in atomic layer deposition of silicon dioxide film in gap fill applications

Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.

Flowable oxide film with tunable wet etch rate

A semiconductor processing gas flow manifold is provided that allows for the gas flow characteristics of the manifold gas flow paths to be individually adjusted outside of a semiconductor processing chamber. The gas flow manifold may be connected to a process gas dispersion device inside the semiconductor processing chamber. The process gas dispersion device may have multiple gas flow channels, each channel separately connected to a manifold gas flow path and targeted at a region on the semiconductor wafer. The adjustment of the individual manifold gas flow paths may vary the amount of process gas dispersed through each process gas dispersion gas flow channel onto the corresponding region of the semiconductor wafer.

Apparatus and method for improving wafer uniformity

Novel gap fill schemes involving depositing both flowable oxide films and high density plasma chemical vapor deposition oxide (HDP oxide) films are provided. According to various embodiments, the flowable oxide films may be used as a sacrificial layer and/or as a material for bottom up gap fill. In certain embodiments, the top surface of the filled gap is an HDP oxide film. The resulting filled gap may be filled only with HDP oxide film or a combination of HDP oxide and flowable oxide films. The methods provide improved top hat reduction and avoid clipping of the structures defining the gaps.

Gap fill integration

Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the deposited nucleation layer prior to depositing the bulk tungsten fill. The treatment operation lowers resistivity of the deposited tungsten film. In certain embodiments, the depositing the nucleation layer involves a boron-based chemistry in the absence of hydrogen. Also in certain embodiments, the treatment operations involve exposing the nucleation layer to alternating cycles of a reducing agent and a tungsten-containing precursor. The methods are useful for depositing films in high aspect ratio and/or narrow features. The films exhibit low resistivity at narrow line widths and excellent step coverage.

Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics

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Cupertino, CA, United States of America

Kaihan Abidi Ashtiani