Cypress Semiconductor Corporation

Kaichiu Wong

Yongchul Ahn

Krishnaswamy Ramkumar

Bo Jin

Venuka K Jayatilaka

Suraj Puri

Raj Mohindra

Hanna Bamnolker

Rajiv Bhushan

Oliver Pohland

David C Wong

Ahmad Chatila

Gregory M McMahon

Gary Elmore

A semiconductor structure has a substrate having a trench, an isolation dielectric in the trench, and a stress buffer layer, between the substrate and the dielectric. Semiconductor devices containing the semiconductor structure may have higher reliability, and may have a reduced manufacturing costs per device.

Isolation technology for submicron semiconductor devices

A semiconductor device memory cell () can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell () can include a first inverter () and second inverter () arranged in a cross-coupled configuration. A capacitor () can be coupled between a first storage node () and second storage node (). A capacitor () can be a 'built-in' capacitor formed with interconnect wirings utilized to connect memory cell circuit components.

Soft error resistant memory cell and method of manufacture

A method and process reducing or eliminating electrical leakage between active areas in a semiconductor separated by isolation regions. A method and process are disclosed for the fabrication of an isolation region in a semiconductor. The method and process can be used in the fabrication of isolation regions used for the separation of adjacent active areas in an integrated circuit. A shallow trench is created on the surface of the semiconductor in regions where isolation spaces are to be formed. A layer of silicon dioxide (LINOX) is then grown over the surfaces of the trench. The LINOX covers roughened regions formed along the surfaces of the trench during its formation. The LINOX is then annealed at a temperature above the LINOX deposition temperature for a period of time. Annealing reduces stresses in the LINOX and in the surrounding semiconductor material. Annealing also increases the density of the LINOX. Thus annealing increases the LINOX resistance to gouge during subsequent processing. This leads to a reduction in dislocations in the semiconductor and a reduction in electrical leakage around the isolation region. A more robust LINOX and a reduction in electrical leakage around an isolation region allows the further shrinkage of integrated circuit dimensions. Furthermore, denuding and gettering of the semiconductor are both accomplished during the annealing step which results in a shortening of total processing time. Finally, since gouging of the LINOX no longer occurs where poly/spacer etch overlaps an active area corner, restrictions on placement of poly lines have been eliminated.

Process for reducing leakage in an integrated circuit with shallow trench isolated active areas

According to one embodiment, a structure for monitoring a process step may include an etch stop layer ( ) formed on a substrate ( ) and a trench emulation layer ( ) formed over an etch stop layer ( ). Monitor trenches ( ) may be formed through a trench emulation layer ( ) that terminate at an etch stop layer ( ). Monitor trenches ( ) may have a depth equal to a trench emulation layer ( ) thickness. A trench emulation layer ( ) thickness may be subject to less variation than a substrate trench depth. A monitor structure ( ) may thus be used to monitor features formed by one or more process steps that may vary according to trench depth. Such process steps may include a shallow trench isolation insulator chemical mechanical polishing step. In addition, or alternatively, a monitor structure ( ) may be formed on a non-semiconductor-on-insulator (SOI) wafer, but include SOI features, providing a less expensive alternative to monitoring some SOI process steps.

Structure and method for monitoring a semiconductor process, and method of making such a structure

A method of forming a semiconductor structure is described that includes etching a first metal layer at the bottom of a via in a first insulating layer to expose a second metal layer, wherein the first metal layer is on the second metal layer, and wherein the etching of the first metal layer is not reactive-ion etching. Methods of making semiconductor devices and electronic devices are also described.

Methods of forming semiconductor structures, and articles and devices formed thereby

A process for making a semiconductor structure, includes forming a second dielectric layer on exposed regions of an intermediate structure. The intermediate structure includes: a semiconductor substrate having the regions, a first dielectric layer on at least a first portion of the semiconductor substrate, an etch-stop layer on at least a second portion of the first dielectric layer, and spacers on at least a third portion of said semiconductor substrate. The spacers are adjacent edges of the etch-stop layer and adjacent the exposed regions.

Contact structures, methods for forming contact structures, and masks for forming contact structures are disclosed. According to one embodiment a contact hole ( ) may be formed with a contact hole mask ( ) that may have a generally rectangular shape and include corner extensions ( - to - ) and side indents ( - to - ). A long side of a contact hole ( ) may be aligned in the same direction as an active area ( ). A contact hole ( ) may be situated between a first portion ( - ) and a second portion ( - ) of an intermediate structure ( ). Alternate embodiments can include a &ldquo;cactus&rdquo; shaped intermediate structure ( ) that may be formed with an intermediate structure mask having corner indents ( ).

Contact structure and method of forming a contact structure

Water vapor plasma etching of metal surfaces facilitates removal of organic residues over metal surfaces. By plasma etching metal surfaces covered with an organic material, such as photoresist, in an atmosphere in which the water vapor to O ratio exceeds 5:3 (such as about 5:1, for example), superior organic material removal results are observed, particularly over relatively wide metal surfaces. The duration of the water vapor plasma etch also may be increased, relative to conventional organic material-removing processes. The effectiveness of the high vapor etch according to the present invention allows the elimination of a subsequent dry organic material stripping step, reducing processing time and cost while increasing yields.

High vapor plasma strip methods and devices to enhance the reduction of organic residues over metal surfaces

A method is described for cleaning a semiconductor wafer. The method includes immersing a wafer in a liquid comprising water. The wafer has a front face, a back face, and an edge. The method also includes providing a substantially particle free environment adjacent to the front face and the back face as the liquid is being removed. A step of introducing a carrier gas comprising a cleaning enhancement substance also is included. It is believed that the cleaning enhancement substance dopes any liquid adhered to the front and back faces of the wafer to cause a concentration gradient of the cleaning enhancement substance in the liquid and accelerate removal of the adhered liquid off of the water.

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Sunnyvale, CA, United States of America

Kaichiu Wong