Xilinx, Inc.

Cadence Design Systems, Inc.

Actel Corporation, Inc.

Triscend Corporation

Kai Zhu

Sridhar Krishnamurthy

Bart Reynolds

Damon McCormick

Volker Hecht

Zhiyong Wang

Cheng-I Chuang

Ankush Sood

Tom Shui

Chukwuweta Chukwudebe

David John Seibert

Tsuwei Ku

Huey-Yih Wang

Hua Song

Yu-Fang Chung

Disclosed approaches for pipelining signal paths in an integrated circuit (IC) device include receiving by a design tool a circuit design to be implemented in the integrated circuit device. The design tool identifies signals of the circuit design that require pipeline registers between drivers and loads of the signals, and relaxes an initial timing requirement to a relaxed timing requirement. The design tool determines respective numbers of pipeline registers to insert between each driver and load of each of the signals based on the relaxed timing requirement. The design tool inserts in the circuit design, respective sets of the respective numbers of pipeline registers between each driver and load of each of the signals. The design tool places the respective sets of the pipeline registers on the IC device using the initial timing requirement.

Insertion and placement of pipeline registers in signal paths of an integrated circuit

In one embodiment of the invention, a method of synthesizing physical gates from register transfer logic code for an integrated circuit design is disclosed. The method includes reading a register transfer level (RTL) input file describing an integrated circuit design; parsing and translating the RTL input file into a plurality of Boolean logic equations; translating the plurality of Boolean logic equations into a plurality of logic primitives; placing the plurality of logic primitives into a floorplan of the integrated circuit design, wherein the placement of the plurality of logic primitives defines wire interconnects; and optimizing each of the plurality of Boolean logic equations in response to wire costs and wire timing delays.

Physically aware logic synthesis of integrated circuit designs

A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprises creating a timing graph; computing minimum delay tuples for nodes in the timing graph; if there is not at least one feasible delay tuple, determining a longest path and computing minimum delay tuples for the longest path; changing polarities on the longest path to reduce delays; updating the timing graph by transferring new polarity and delay values; performing timing analysis to determine a new longest path if the new longest path is shorter than the prior longest path, accepting a resulting polarity selection and computing minimum delay tuples for the longest path; if the new longest path is not shorter than the prior longest path, accepting a resulting polarity selection and implementing changes in a user-program bitstream.

Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit

In one embodiment, a method for specifying addressability in a memory-mapped device is disclosed. A data access primitive is used to model addressablity for the memory-mapped device. Addressability comprises an address matching function, a lane matching function and one or more bus connections. A first starting address for the memory-mapped device is specified. A first set of addressing matching function, lane matching function and one or more bus connections for the memory-mapped device is generated using the data access primitive and the first starting address.

Method and apparatus for specifying addressability and bus connections in a logic design

Method and apparatus for specifying address offsets and alignment in logic design

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Palo Alto, CA, United States of America

Kai Zhu