Lsi Logic Corporation

Cisco Technology, Inc.

E-tek Dynamics, Inc.

Infineon Technologies Ag

Alliance Fiber Optics Products, Inc.

Arasor Corporation

Kai Zhang

Johnu George

Debojyoti Dutta

Yonglin Huang

Yathiraj B Udupi

Philippe Schoenborn

J J Pan

Wilbur G Catabay

Marc Solanas Tarre

Wei-Jen Hsia

Keith K Chao

Manoj Sharma

Shumay X Dou

Hong-Qiang Lu

Yong-Bae Kim

Dilip Vijay

Masaichi Eda

Kiran Kumar

Rongxiang Hu

Yongbae Kim

Sang-Yun Lee

Hiroaki Takikawa

Sarah Neuman

Jing-Jong J Pan

Zhihai Wang

Jonathan James Ashley

Richard D Schinella

Peter C Chang

Heinrich J Stockmanns

Aparupa Das Gupta

John Rongxiang Hu

Amit Agarwal

Seth Mason

Senthil Arthanari

Shou-Jong Sheih

Dennis Chi Zhou

Embodiments include receiving an indication of a data storage module to be associated with a tenant of a distributed storage system, allocating a partition of a disk for data of the tenant, creating a first association between the data storage module and the disk partition, creating a second association between the data storage module and the tenant, and creating rules for the data storage module based on one or more policies configured for the tenant. Embodiments further include receiving an indication of a type of subscription model selected for the tenant, and selecting the disk partition to be allocated based, at least in part, on the subscription model selected for the tenant. More specific embodiments include generating a storage map indicating the first association between the data storage module and the disk partition and indicating the second association between the data storage module and the tenant.

Tenant-level sharding of disks with tenant-specific storage modules to enable policies per tenant in a distributed storage system

Approaches are disclosed for improving performance of logical disks. A logical disk can comprise several storage devices. In an object storage system (OSS), when a logical disk stores a file, fragments of the file are stored distributed across the storage devices. Each of the fragments of the file is asymmetrically stored in (write) and retrieved from (read) the storage devices. The performance of the logical disk is improved by reconfiguring one or more of the storage devices based on an influence that each of the storage devices has on performance of the logical disk and the asymmetric read and write operations of each of the storage devices. For example, latency of the logical disk can be reduced by reconfiguring one or more of the plurality of storage disks based on a proportion of the latency of the logical device that is attributable to each of the plurality of storage devices.

Performance of object storage system by reconfiguring storage devices based on latency that includes identifying a number of fragments that has a particular storage device as its primary storage device and another number of fragments that has said particular storage device as its replica storage device

Embodiments include obtaining at least one system metric of a distributed storage system, generating one or more recovery parameters based on the at least one system metric, identifying at least one policy associated with data stored in a storage node of a plurality of storage nodes in the distributed storage system, and generating a recovery plan for the data based on the one or more recovery parameters and the at least one policy. In more specific embodiments, the recovery plan includes a recovery order for recovering the data. Further embodiments include initiating a recovery process to copy replicas of the data from a second storage node to a new storage node, wherein the replicas of the data are copied according to the recovery order indicated in the recovery plan.

Smart storage recovery in a distributed storage system

A method for assisting evaluation of anomalies in a distributed storage system is disclosed. The method includes a step of monitoring at least one system metric of the distributed storage system. The method further includes steps of maintaining a listing of patterns of the monitored system metric comprising patterns which previously did not result in a failure within one or more nodes of the distributed storage system, and, based on the monitoring, identifying a pattern (i.e., a time series motif) of the monitored system metric as a potential anomaly in the distributed storage system. The method also includes steps of automatically (i.e. without user input) performing a similarity search to determine whether the identified pattern satisfies one or more predefined similarity criteria with at least one pattern of the listing, and, upon positive determination, excepting the identified pattern from being identified as the potential anomaly.

Correctly identifying potential anomalies in a distributed storage system

An improved Viterbi detector is disclosed in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. Also disclosed is a method of reducing the complexity of the branch metric calculations by clustering branches corresponding to signals with similar signal-dependent noise statistics. A feature of this architecture is that the branch metrics are clustered into multiple groups, where all the members of each group draw input from a single, shared noise predictive filter corresponding to the group. In recording technologies as practiced today, physical imperfections in the representation of recorded user data in the recording medium itself are becoming the dominate source of noise in the read back data. This noise is highly dependent on what was (intended to be) written in the medium. The disclosed Viterbi detector exploits this statistical dependence of the noise on the signal.

Method and apparatus for a data-dependent noise predictive viterbi

A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Method of preventing resist poisoning in dual damascene structures

A method of processing a substrate, where the substrate is transferred from an ambient environment into a clean environment. The substrate is heated to at least a first temperature within the clean environment, and then maintained at no less than the first temperature within the clean environment. The substrate is selectively transferred within the clean environment to more than one processing chambers, and processed in the more than one processing chambers. The substrate is transferred from the clean environment into the ambient environment.

In situ liner barrier

The present invention is directed towards a channel power monitor for monitoring channel power levels for each of N signal channels. The value of each channel power level is designated as p(&lgr; ), where &lgr; is a channel parameter that characterizes each channel. An embodiment of the invention includes a variable channel attenuator having M attenuation profiles where M&gE;N, and where a k-th attenuation profile is characterized as a function of the channel parameter &lgr; by A (&lgr; ). This embodiment also includes a detector for measuring a k-th integrated attenuated power level, the value of which is represented by P . An analysis unit receives all of the values P of the integrated attenuated power levels and thereupon derives the values p(&lgr; ) of the channel power levels by solving a set of linear equations.

Channel power monitor

Via poisoning of vias formed in low k carbon-containing silicon oxide dielectric material is suppressed by forming the via in a layer of such dielectric material with a smooth inwardly sloped sidewall. Such a sloped sidewall via can be etched in a low k dielectric layer by first forming a via resist mask over the upper surface of such a dielectric layer, then heat treating the mask sufficiently to deform the sidewall geometry of the resist mask to form a sloped sidewall on the opening or openings in the heat treated resist mask. The resulting erosion of such a resist mask, during a subsequent etch step to form the via in the low k dielectric material through such a sloped sidewall resist mask, imparts a tapered or sloped sidewall geometry to the via which is then formed in the underlying layer of low k dielectric material. In a preferred embodiment, when the via is cut through several layers of different types of dielectric material, the smoothness of the sloped sidewall of the resulting via is enhanced by adjusting the selectivity of the via etch to uniformly etch each of the layers of dielectric material at approximately the same rate.

Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning

Protective caps are formed over horizontally closely spaced apart metal lines of an integrated circuit structure. Low k silicon oxide dielectric material is then deposited over and between the metal lines and over protective caps on the lines. After the formation of such low k material between the lines and over the caps, standard k dielectric material is deposited over the low k layer as a planarizing layer over low portions of the low k layer between the lines which may be lower than the top of the caps on the lines to prevent further etching or dishing of the low k layer of during planarizing. The structure is then planarized to bring the low k dielectric material down to the tops of the protective caps on the metal lines. A layer of standard k silicon material is then formed over the planarized low k layer and the caps to allow via formation without passing through the low k layer to avoid via poisoning.

Processing for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines

A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus. The substrate is then solvent cleaned to remove etch residues and then annealed to degasify the low k dielectric material. The substrate is then RF cleaned and a thin layer of PVD titanium is then formed in the same chamber over the surfaces of the openings. CVD titanium nitride is then formed over the titanium in the same vacuum apparatus. The coated openings are then filled with aluminum, tungsten, or copper.

Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning

A composite layer of low k dielectric material for integrated circuit structures comprising a thick lower conformal barrier layer of low k dielectric material, a low k center layer of carbon-doped silicon oxide dielectric material having good gap filling capabilities, and a thick upper conformal barrier layer of low k dielectric material. The thick lower conformal barrier layer of low k dielectric material protects the lower surface of the main low k dielectric layer and also protects against misaligned vias entering the main low k dielectric material below the height of the metal line without raising the capacitance of the structure as would a lower barrier layer of non-low k dielectric material. The thick upper conformal barrier layer of low k dielectric material protects the upper surface of the main low k dielectric layer, as well as to provide thickness for vias to pass through without risk of via poisoning, and without raising the capacitance of the structure as would a thick upper barrier layer of non-low k dielectric material.

Composite low dielectric constant film for integrated circuit structure

Growing community of inventors

San Jose, CA, United States of America

Kai Zhang