Taiwan Semiconductor Manufacturing Comp. Ltd.

Kai-Yun Lin

Chin-Yuan Huang

Chewn-Pu Jou

Shuo-Mao Chen

Feng Wei Kuo

Ho-Hsiang Chen

Chung-Hsing Wang

Chih Sheng Tsai

Ying-Lin Liu

Po-Hsiang Huang

Yi-Kan Cheng

Chin-Chou Liu

Fong-Yuan Chang

Chin-Her Chien

Cheng-Hung Yeh

Kai-Ming Liu

Yao-Hsien Tsai

Tai-Yu Wang

Ming-Ke Tsai

A method of verifying an integrated circuit stack includes adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate. The method further includes converting the first dummy layer location to the connecting substrate. The method further includes adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad. The method further includes performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.

Integrated circuit stack verification method and system for performing the same

A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.

A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.

Package structure and method for forming the same

A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes determining whether the dummy layer is aligned with the contact pad of the connecting substrate. The method further includes adjusting the dummy layer location in the functional circuit when the dummy layer location is misaligned with the contact pad of the connecting substrate.

A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate; and determining whether the dummy layer is aligned with the contact pad of the connecting substrate. The method further includes performing an LVS check of the connecting substrate including the dummy layer; and adjusting the dummy layer location in the functional circuit if the dummy layer location is misaligned with the contact pad of the connecting substrate or the connecting substrate fails the LVS check. The method further includes repeating the converting step, the determining step, and the performing the LVS check step based on the adjusted dummy layer location.

A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.

Verification of 3D integrated circuits

A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices.

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Hsinchu, Taiwan

Kai-Yun Lin