Realtek Semiconductor Inc.

Kai-Yue Lin

Wei-Jyun Wang

Shih-Hsiung Huang

Kai-Yin Liu

Liang-Wei Huang

Hsuan-Ting Ho

Hsuan-ting Ho

Chi-Hsi Su

Sheng-Yen Shih

Kuei-Ying Lu

Yu-Ting Chiu

Jian-ru Lin

An analog front-end device includes an amplifier circuit, a first gain control circuit, and a tracking circuit. The amplifier circuit is configured to generate a first output signal according to a first input signal. The first gain control circuit is configured to set a first electronic component according to a first gain control signal and transmit the first input signal to a first input terminal of the amplifier circuit via the first electronic component, in which a terminal of the first electronic component is selectively coupled to the first input terminal or a first predetermined node. The tracking circuit is configured to adjust a level of the first predetermined node according to a level of the first input terminal, in order to reduce a voltage difference between the first input terminal and the first predetermined node.

Analog front-end device

A calibration method of a pipeline analog-to-digital converter (ADC) that includes a residue amplifier includes the following steps: (A) generating an offset voltage; (B) adjusting a first input voltage of the residue amplifier according to the offset voltage and a reference digital code; (C) converting an output voltage of the residue amplifier into a second digital code; (D) performing a correlation operation on the reference digital code and the second digital code to generate an intermediate gain; (E) recording the intermediate gain; (F) repeating step (A) to step (E) to record a plurality of intermediate gains; (G) selecting one of the intermediate gains as a digital gain according to the second digital code; and (H) generating an output digital code according to a first digital code, the reference digital code, the digital gain, and the second digital code.

Pipeline analog-to-digital converter and calibration method thereof

The present invention discloses a DAC method having signal calibration mechanism used in a DAC circuit having thermometer-controlled current sources generating an output analog signal according to a total current thereof and a control circuit. Current offset values of the current sources are retrieved. The current offset values are sorted to generate a turn-on order, in which the current offset values are separated into current offset groups according to the turn-on order, the signs of each neighboring two groups being opposite such that the current offset values cancel each other when the current sources turn on according to the turn-on order to keep an absolute value of a total offset not larger than a half of a largest absolute value of the current offset values. The current sources are turned on based on the turn-on order according to a thermal code included in an input digital signal.

Digital-to-analog conversion circuit and method having signal calibration mechanism

The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.

Analog to digital conversion apparatus and method having quick conversion mechanism

An analog-to-digital converter includes a switch circuit, a first capacitor array, a second capacitor array and a comparator. A method of operating the analog-to-digital converter includes switching a swap signal to a first level in a first sampling period for the switch circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and couple the second capacitor array to a second input terminal of the comparator and a second signal source, and switching the swap signal to a second level in a second sampling period for the switch circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and couple the second capacitor array to the first input terminal of the comparator and the first signal source.

Analog-to-digital converter capable of reducing nonlinearity and method of operating the same

A method of operating an analog-to-digital converter includes in a first conversion period, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitor of a first capacitor array, and a second selection circuit switching a voltage output to a second capacitor of a set of larger capacitor of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generating a second comparison result different from the first comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitor of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitor of the second capacitor array.

Method of operating analog-to-digital converter by reversed switching technique and analog-to-digital converter utilizing same

A method of operating an analog-to-digital converter includes in a first sampling stage, switching a swap signal to a first level for a first selection circuit to reset a first capacitor array according to a first voltage configuration and for a second selection circuit to reset a second capacitor array according to the first voltage configuration, and in a second sampling stage, switching the swap signal to a second level for the first selection circuit to reset the first capacitor array according to the second voltage configuration and for the second selection circuit to reset the second capacitor array according to the second voltage configuration. A control logic circuit is used to switch the swap signal between the first level and the second level in a uniform order in a plurality of sampling stages.

Analog-to-digital converter and method of operating same

A method and a measuring apparatus for measuring noise of a device under test (DUT) is provided, wherein the DUT is connected to a link partner (LP) device via a cable, and the measuring apparatus is coupled to the DUT and LP device. The method includes: controlling the LP device to transmit a far-end data sequence to the DUT according to transmission data; controlling the DUT to recover the transmission data for generating aided-data sequence according to the transmission data, wherein the aided-data sequence is configured to perform cancellation with a received far-end data sequence to generate a cancellation result; generating a first noise value and a second noise value in a first training phase and a second training phase, respectively; and estimating noise from at least one circuit according to the first noise value and the second noise value.

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Hsinchu, Taiwan

Kai-Yue Lin