Taiwan Semiconductor Manufacturing Comp. Ltd.

Kai-Yuan Ting

Sandeep Kumar Goel

Yun-Han Lee

Ashok Mehta

Stanley John

Tze-Chiang Huang

Mei Hsu Wong

Chao-Yang Yeh

Hsin-Cheng Chen

Shereef Shehata

Charlie Zhou

Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.

Function safety and fault management modeling at electrical system level (ESL)

A method for dynamic frequency scaling (DFS) on the electronic systems level (ESL). The method can run in a virtual environment and dynamically scale the frequency of a virtual component based on a first transaction time and a second transaction time.

Dynamic frequency scaling

A device for power estimation is disclosed. The device includes a transformer circuit coupled with a processing circuit and a transaction interface. The transformer circuit is configured to count performance activities executed in the processing circuit and to compare count values of the performance activities with a predetermined value to determine a power state of the processing circuit. The transaction interface is configured to receive a request from the processing circuit and record a first timestamp, and further configured to receive a response from a memory model and record a second timestamp, the transaction interface being further configured to record a time difference between the first timestamp and the second timestamp as a time difference. The transformer circuit is further configured to determine the power state of the processing circuit based on both of the count values and the time difference.

Power estimation

Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation of various loads on one or more batteries of an electronic device resulting from the electronic device performing one or more functional behaviors. Before this electronic simulation occurs, the electronic device is modeled using the high-level software language or the high-level software format. For example, a battery discharge model, a regulator efficiency model, a power delivery network (PDN) model, or a component power model are used to model behaviors of the one or more batteries, regulator circuitry, power delivery network (PDN) circuitry, and other electronic circuits, respectively, of the electronic device. After completion of the modeling of the electronic device, the ESL design and verification of the present disclosure utilizes a simulation algorithm, in conjunction with the high-level software model of the electronic device to simulate the discharge of electrical energy of the one or more batteries.

Electrical system level (ESL) battery discharge simulation

A method includes receiving a source code for executing a plurality of operations associated with a machine learning algorithm, classifying each operation into a fast operation group or a slow operation group, defining a neuron network for executing operations of the slow operation group, and mapping the neuron network to an initial machine learning hardware configuration. The method also includes executing operations of the slow operation group on the initial machine learning hardware configuration, modifying the initial machine learning hardware configuration in response to a determination that the slow group operation fails to produce an expected result in response to at least one set of inputs; and executing a fast group operation using a machine learning software code.

System and method for ESL modeling of machine learning

A method is disclosed that includes providing an IP bank, an application bank, and a technology bank; generating a hierarchical table based on the IP bank and the application bank; performing an estimation of at least one of a performance value, a power value, an area value and a cost value, which corresponds to the hierarchical table, by using the technology bank, to output an result data as a basis of fabrication of a system.

System and method for system-level parameter estimation

A power state transformer, a system and a method thereof are disclosed. The power state transformer is coupled with a processing unit model. The power state transformer is configured for counting performance activities executed in the processing unit model, and further for determining a power state of the processing unit model according to count values of the performance activities.

A method of estimating power consumption of a processor includes accessing an electronic system level (ESL) model of the processor, the ESL model including a plurality of functional blocks, identifying a plurality of processor events by tracing activity of the plurality of functional blocks for a plurality of machine code instructions, and calculating a first power consumption value based on the plurality of processor events. The method also includes identifying a plurality of cycles by analyzing a plurality of micro-code operation codes corresponding to the plurality of machine code instructions, calculating a second power consumption value based on the plurality of cycles, and calculating a total power consumption value from the first power consumption value summed with the second power consumption value.

Processor power estimation

A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

System and method for validating stacked dies by comparing connections

Provided is a system that includes a monitoring unit, processing units, and peripheral units. Each of the processing units is linked to the monitoring unit and each of the peripheral units is also linked to the monitoring unit. Each of the processing units is configured to transmit requests to and subsequently receive responses from at least one of the peripheral units through the monitoring unit. The monitoring unit is configured to measure and store delays between the responses and the respective requests.

System and method of adaptive voltage frequency scaling

A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output ('IO') trace from a die verification test from a first format to a second format to improve performance.

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San Jose, CA, United States of America

Kai-Yuan Ting