Au Optronics Corporation

Kai-Yuan Siao

Jian-Feng Li

Chun-Hsien Lin

Chien-Liang Chen

Chao-Ching Hsu

Yi-Suei Liao

Chun-Kuei Wen

Hsiao-Chung Cheng

Tsung-Hung Lee

Shih-Yuan Su

Yi-Hao Wang

Tien-chin Huang

Kuo-Hsiang Chien

Hsin-Ting Wu

A data driver for a display device comprises a first boost circuit, a first gate clock generation circuit, a first level shift circuit, and a data drive circuit. The first boost circuit is used to receive a supply voltage value and generate at least one preset voltage value. The first gate clock generation circuit is electrically coupled to the first boost circuit, and is used to receive a plurality of timing signals and at least one preset voltage value, and generate at least one first timing signal. The first level shift circuit is used to receive the at least one first timing signal and generate at least one gate timing signal. The data drive circuit is used to receive the timing signals, and generate a plurality of display data signals.

Display device and data driver

A display apparatus and an operation method thereof are provided. The display apparatus includes a display panel. The display panel includes a plurality of data lines, a plurality of scan lines and a plurality of pixels. The pixels are arranged in a matrix manner, and each pixel is electrically connected to one of the data lines and one of the scan lines. The operation method includes steps of: dividing the scan lines into N scan line groups, wherein N is an integer from 2 to the number of the scan lines; and in N frame periods sequentially driving the N scan line groups of scan line respectively and thereby sequentially updating display data of the pixels electrically connected to the N scan line groups of the scan line respectively.

Partially-driven display apparatus

A gate output control method is adapted into a flat display having a plurality of gate drive integrated circuits. The method comprises: providing a gate control signal; providing a oblique control signal to oblique modulate the gate control signal for generating a gate control signal with oblique; modulating the gate control signal with oblique to obtain a modulated gate control signal; and outputting the modulated gate control signal to the gate drive integrated circuits. A falling edge of the modulated gate control signal comprises a oblique-varying period and a vertical-varying period. In the oblique-varying period, the modulated gate control signal firstly changes to a predetermined voltage in a first slope, and then changes in a second slope until the vertical-varying period. In the vertical-varying period, the modulated gate control signal changes vertically or nearly vertically.

Gate output control method and corresponding gate pulse modulator

An electro-static discharge (ESD) protection structure includes a first insulation layer (having a first surface, a second surface opposite to the first surface, and a through hole), a patterned conductive layer (located on the first surface), an electro-static releasing layer (located on the second surface), and a solder mask layer. At least one portion of the patterned conductive layer surrounds the through hole. The electro-static releasing layer is electrically insulated from the patterned conductive layer. At least one portion of the electro-static releasing layer is around the through hole. The solder mask layer covers the first insulation layer and a portion of the patterned conductive layer and exposes a portion of the patterned conductive layer surrounding the through hole. A multi-layered circuit board including a second insulation layer, a power supply layer, a third insulation layer and the ESD protection structure is also provided.

Multi-layered circuit board and electro-static discharge protection structure

A display apparatus with a display panel is provided. The display panel is initially driven to have the data voltages on any two consecutive data lines thereon with different polarities. If a to-be-displayed image contains a predetermined pattern constituted by pixels in row and two adjacent pixels therein have a gray-level difference therebetween greater than a predetermined value, a timing control circuit of the display apparatus divides the associated data lines into a plurality of data line groups each constituted by four consecutive data lines and configure the data voltages on the two middle data lines in one data line group to have a first polarity and the data voltages on the rest two data lines in the same data line group to have a second polarity. An operation method of the display apparatus is also provided.

Display apparatus and operation method thereof

A flat display device includes an array substrate. The array substrate includes a plurality of gate lines, data lines and pixels. The pixels include a plurality of first pixel units and second pixel units, and each of the first pixel units and each of the second pixel units include more than three pixels. The first pixel units and the second pixel units disposed in between two adjacent data lines are arranged alternately, wherein the first pixel units are electrically connected with one of the two adjacent data lines, and the second pixel units are electrically connected with the other data line.

Growing community of inventors

Hsin-Chu, Taiwan

Kai-Yuan Siao