Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Kai-Yu Peng

Yen-Teng Ho

Chenming Hu

Shu-Jui Chang

Chen-Han Chou

Chia-Hsing Wu

Cheng-Hung Shen

Chen Han Chou

Cheng Hung Shen

Chia Hsing Wu

A device comprises a plurality of 2D semiconductor nanostructures, a gate structure, a source region, and a drain region. The plurality of 2D semiconductor nanostructures extend in a first direction above a substrate and arranged in a second direction substantially perpendicular to the first direction. The gate structure surrounds each of the plurality of 2D semiconductor nanostructures. The source region and the drain region are respectively on opposite sides of the gate structure.

Transistors having two-dimensional semiconductor channels

A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.

Three dimensional integrated circuit and fabrication thereof

An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.

Growing community of inventors

Miaoli County, Taiwan

Kai-Yu Peng