Dsc Communications Corporation

Kai Y Yang

P Kingston Duffie

Ross M Schibler

An ingress processor (16) includes an ingress controller (34) that controls the flow of asynchronous transfer mode (ATM) cells placed in the ingress cell memory (32) by a cell loader (30). The ingress controller (34) links together ATM cells within the ingress cell memory (32) that correspond to a particular packet. The ingress controller (34) sends the beginning of message cell (BOM) to a route cell buffer (42) for processing by an ingress router (44). The ingress router (44) determines routing information from content addressable memories (72) and routed cache associative memory (73) corresponding to the BOM cell within the route cell buffer (42). A router controller (60) within the ingress router (44) generates a setup ATM cell containing the retrieved routing information and sends the setup ATM cell to the ingress processor (34) through the route cell buffer (42). The ingress processor (34) sends the setup cell, the BOM cell, a transmit agent (48) through a transmit agent cell buffer (46) for transmission out of the ingress processor (16). The transmit agent (48) transmits all subsequent cells of the packet. Routing information for the packet is also stored in a VCI table (50) for use by the transmit agent (48) such that further route determinations for subsequent cells within a packet need not be determined by the ingress router (44).

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Cupertino, CA, United States of America

Kai Y Yang