Intel Corporation

Kai Xiao

Michael Apodaca

Abhishek R Appu

Joydeep Ray

Prasoonkumar Surti

Ankur N Shah

Altug Koker

Carson Brownlee

Travis T Schluessler

Adam T Lake

Hugues Labbe

Jeffery S Boles

Thomas F Raoux

Elmoustapha Ould-Ahmed-Vall

Nikos Kaburlasos

Deepak Shashidhar Vembar

Chandrasekaran Sakthivel

Joshua D Barczak

Atsuo Kuwahara

Gong Ouyang

Balaji Vembu

Tomer Bar-On

Carsten Benthin

Gabor Liktor

James M Holland

Jacek Kwiatkowski

Gokcen Cilingir

Kamal Sinha

Narayan Biswal

Abhishek Venkatesh

Radhakrishnan Venkataraman

Xiaoning Ye

Slawomir Grajewski

Beom-Taek Lee

Jason Daniel Tanner

Zuoguo Wu

Stanley J Baran

Wenyin Fu

Xiang Li

Bhushan M Borole

John G Gierach

Barnan Das

Archie Sharma

Mayuresh M Varerkar

Karthik Vaidyanathan

Zhichao Zhang

John H Feit

Jonathan Kennedy

Philip R Laws

Nilesh V Shah

Tomasz Janczak

David M Cimini

Louis Feng

Sayan Lahiri

Jill MacDonald Boyce

Kemal Aygun

Pattabhiraman K

Josh B Mastronarde

Shaowu Huang

Jeffrey Tripp

Subramaniam M Maiyuran

Debendra Das Sharma

Sanjeev S Jahagirdar

Guei-Yuan Lueh

Linda L Hurd

Kiran Chand Veernapu

David M Puffer

Scott R Janus

Devan Burke

Eric Jin Li

Brent E Insko

Sang-hee Lee

Johannes Guenther

Srikanth Potluri

Eric J Asperheim

Anupreet S Kalra

Jong-Ru Guo

Murali Ramadoss

James A McCall

Harry Muljono

Zhen Zhou

Jong Dae Oh

Andrew T Lauritzen

Sameer Kp

Jefferson Amstutz

Vivek Tiwari

Tzach Ashkenazi

Yunhui Chu

Jun Liao

Maria Bortman

Venkatraman Iyer

Peter L Doyle

Yuan-Liang Li

Jiangqi He

Huimin Chen

Howard L Heck

Hao-Han Hsu

Jaejin Lee

Kenneth Foust

Yun Ling

In one embodiment, a card edge connector includes a housing including a slot to receive a first circuit board. A first plurality of pins extend from within the slot through a bottom of the housing. Each of the first plurality of pins includes a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a first plurality of contacts of a second circuit board, the second end including a heel portion and a toe portion extending from the heel portion in a direction away from a centerline of the slot. A second plurality of pins extend from within the slot through the bottom of the housing. Each of the second plurality of pins includes a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a second plurality of contacts of the second circuit board, the second end comprising a heel portion and a toe portion extending from the heel portion in a direction toward the centerline of the slot. Other embodiments are described and claimed.

Card edge connector including a flipped pin foot orientation

An apparatus comprises a crosstalk cancelation circuit comprising a plurality of taps to output signals based on a signal transmitted via a first data line; and a summation circuit to combine a signal received by a second data line with the signals output by the plurality of taps to reduce near-end crosstalk present in the signal received by the second data line.

Near-end crosstalk cancellation system

In one embodiment, a card edge connector includes: a housing having an opening into which a first circuit board is to be inserted; a plurality of pins each having a first end and a second end, the plurality of pins extending from within the opening through a bottom surface of the housing, the first end of the first plurality of pins to mate with a corresponding contact of the first circuit board; and a plurality of ball grid array (BGA) solder balls each adapted at the second end of a corresponding one of the plurality of pins, the plurality of pins to mate with a corresponding conductive area of a second circuit board to which the card edge connector mates via the plurality of BGA solder balls. Other embodiments are described and claimed.

Ball grid array card edge connector

An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

Apparatus and method for ray tracing instruction processing and execution

Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

Apparatus and method for acceleration data structure refit

A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.

Near field wireless communication system for mother to package and package to package sideband digital communication

An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.

Graphics anti-aliasing resolve with stencil mask

Microelectronic assemblies, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a microelectronic device having a hexagonal node configuration, wherein the hexagonal node configuration may include a differential signal node pair; a power node; and a plurality of ground nodes; and wherein the differential signal node pair, the power node, and the plurality of ground nodes are arranged in a hexagonal parallelogon pattern, wherein the differential signal node pair includes a first differential signal node adjacent to a second differential signal node, and wherein the power node is adjacent and symmetric to the differential signal node pair; and a microelectronic substrate electrically coupled to the microelectronic device.

High speed differential pinout arrangement including a power pin

Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.

Context-aware compression with quantization of hierarchical transform matrices

Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.

Early termination in bottom-up acceleration data structure refit

Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.

Fine feature formation techniques for printed circuit boards

Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.

Sensory enhanced augmented reality and virtual reality device

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Hybrid low power homogenous grapics processing units

Growing community of inventors

San Jose, CA, United States of America

Kai Xiao