Huawei Technologies Co., Limited

Integrated Silicon Solution (Shanghai), Inc.

Zte Corporation

Kai Tao

Mingjie Yin

Qing Chang

Yao Jiang

Haibo Miao

Xiao Jing

Yoh Tz Chang

A sound collecting system includes a first electronic device, a left-ear TWS earphone, and a right-ear TWS earphone. Microphones of the first electronic device, the left-ear TWS earphone, and the right-ear TWS earphone form a first microphone array. When the first electronic device detects a user operation of starting video recording, the first microphone array performs sound collecting to obtain a joint microphone array signal. The first electronic device performs noise reduction processing on the joint microphone array signal.

Sound collecting method, electronic device, and system

A BLUETOOTH communications system includes a true wireless stereo (TWS) BLUETOOTH headset and a terminal device, where the TWS Bluetooth headset includes a first earbud and a second earbud. The terminal device controls the first earbud to collect a sound signal and the second earbud to play a sound signal. When an audio application on the terminal device is started, the first earbud collects a first sound signal, performs sound effect processing on the first sound signal to obtain a second sound signal, and sends the second sound signal to the second earbud. The terminal device sends accompaniment audio to the second earbud, and the second earbud performs audio mixing processing on the accompaniment audio and the second sound signal for playing.

Bluetooth communication method and apparatus

The present invention relates to semiconductor technology, and provides methods for erasing, reading and programming a flash memory. In the present invention, when an erase operation is performed on the flash memory, for a sector selected for the erase operation, its N-type well is applied with a voltage of 8V&#x2dc;12V, its bit line is applied with a voltage of 4V&#x2dc;6V, and its word line is applied with a voltage of &#x2212;7V&#x2dc;&#x2212;10V. When a read operation is performed on the flash memory, for a sector selected for the read operation, its N-type well is applied with a VCC voltage; for a flash memory cell selected for the read operation, its bit line is applied with the VCC voltage, and its source line is applied with a voltage of 0V. When a program operation is performed on the flash memory, for a flash memory cell selected for the program operation, its bit line is applied with a voltage of VCC&#x2212;6.5V&#x2dc;VCC&#x2212;4.5V, and its bit line is applied with a voltage of VCC+6V&#x2dc;VCC+9V. In full consideration of factors including the chip manufacturing process, chip circuit design, chip quality and cost, optimal operating conditions fit for erasing, reading and programming, a NOR-type embedded 2T PMOS flash memory are determined.

Methods for erasing, reading and programming flash memories

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Shanghai, China

Kai Tao