Taiwan Semiconductor Manufacturing Comp. Ltd.

Kai-Ming Chiang

Chih-Wei Lin

Ching-Hua Hsieh

Sheng-Feng Weng

Chao-Wei Li

Yu-Hao Chen

Sheng-Hsiang Chiu

Yi-Da Tsai

Chia-Min Lin

Wei-Lun Tsai

Kai-Fung Chang

Ching-Yao Lin

Ming-Yu Yen

Wei-Jhan Tsai

Hao-Yi Tsai

Yu-Hsiang Hu

Ming Hung Tseng

Tsung-Hsien Chiang

Tzu-Sung Huang

Lipu Kris Chuang

Chun-Yen Lan

Hsaing-Pin Kuan

Ching Yao Lin

Wei Lun Tsai

A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Method of fabricating memory device and package structure

A semiconductor package includes a first redistribution circuit structure, a semiconductor die, and an electrically conductive structure. The semiconductor die is disposed over and electrically coupled to the first redistribution circuit structure. The electrically conductive structure connects a non-active side of the semiconductor die to a conductive feature of the first redistribution circuit structure, where the semiconductor die is thermally coupled to the first redistribution circuit structure through the electrically conductive structure, and the electrically conductive structure includes a structure of multi-layer with different materials.

Semiconductor package with electrically conductive structure and manufacturing method thereof

A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.

Staggered metal mesh on backside of device die and method forming same

A package structure includes a first redistribution circuit structure, a semiconductor die, a connecting film, and a second redistribution circuit structure. The first redistribution circuit structure includes a dielectric structure and a routing structure disposed therein, where the dielectric structure includes a trench exposing the routing structure. The semiconductor die is disposed on and electrically coupled to the first redistribution circuit structure. The connecting film is disposed in the trench and between the semiconductor die and the first redistribution circuit structure, and the semiconductor die is thermally coupled to the routing structure through the connecting film. The second redistribution circuit structure is disposed on and electrically coupled to the semiconductor die, the second redistribution circuit structure is electrically coupled to the first redistribution circuit structure, and the semiconductor die is disposed between the first redistribution circuit structure and the second redistribution circuit structure.

Package structure and manufacturing method thereof

Package structure

Memory device, package structure and fabricating method thereof

A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.

Chip package and method of forming the same

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Hsinchu, Taiwan

Kai-Ming Chiang