Etopus Technology Inc.

Sk Hynix Memory Solutions Inc.

Link a Media Devices Corporation

Lsi Logic Corporation

Agate Logic, Inc.

Kai Keung Chan

Yu Kou

Danfeng Xu

Xin-Ning Song

Marcus Marrow

Kwok Wah Yeung

Jason Bellorado

Haitao Xia

Shih-Ming Shih

Paul K Lai

Ryan Yu

Naveen Kumar

Jung-Sheng Hoei

Kin Man Ng

Xianfeng Rui

Wing Fai Hui

Chao-Chiang Chen

Tze Yin Cheung

Shian-Jiun Fu

Xiaolong Liu

Hon Man Yau

Leo Fang

Pankaj Joshi

David Tsang

A transmitter device having a calibrator circuit is disclosed. The calibrator circuit performs duty cycle calibration and phase calibration on a plurality of clock signals of the transmitter device. In one embodiment, the phase calibration is performed based on a comparison of the clock signals to a reference clock signal from the plurality of clock signals. In another embodiment, the calibrator circuit uses fixed patterns of data signals to perform phase calibration on the plurality of clock signals.

Clock duty cycle calibration and phase calibration for high-speed transmitter

A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.

Receiver for high speed communication channel

A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.

Receiver with adjustable reference voltages

A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.

Multi mode viterbi decoder

Generating error data associated with decoding data is disclosed, including: processing an input sequence of samples associated with data stored on media using a detector and a decoder during a global iteration; and generating one or more error values based at least in part on one or more decision bits output by the detector or the decoder and the input sequence of samples.

Error data generation and application for disk drive applications

A logic processing device, containing an application specific integrated circuit ('ASIC') and field programmable gate array ('FPGA'), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (&#x201c;CLC&#x201d;) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

Method and apparatus for facilitating communication between programmable logic circuit and application specific integrated circuit with clock adjustment

A signal is generated by obtaining an unconstrained random bit sequence. The unconstrained random bit sequence is modified to satisfy a constraint and the modified random bit sequence is output.

Generation of constrained pseudo-random binary sequences (PRBS)

Inter-track-interference correlation and cancellation for disk drive application includes receiving an input sequence of samples; and simultaneously processing the input sequence in at least a detector over one or more iterations while processing the input sequence to produce inter-track-interference information during at least a portion of one of the one or more iterations.

Inter-track interference (ITI) correlation and cancellation for disk drive applications

An initial phase offset between a center track and a side track is determined. An initial side track pulse shape is determined using the initial phase offset and side track interference. The initial side track pulse shape minimizes a contribution of the side track interference to a center track bit. The contribution of the side track interference is removed from the center track bit using the initial side track pulse shape and the side track interference.

Inter-track interference cancelation in the presence of frequency offset

A method for recovering data is disclosed. A sensed analog signal is converted into digital samples using an analog-to-digital converter (ADC). The digital samples are processed into processed digital samples using a first filter. The processed digital samples are decoded into decoded data. Whether the decoded data is acceptable is then determined. The processed digital samples are fed back to the first filter using a reprocessing circuit such that the processed digital samples are reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable. A set of reprocessing coefficients is provided for the first filter to reprocess the processed digital samples.

Data recovery using existing reconfigurable read channel hardware

Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.

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Fremont, CA, United States of America

Kai Keung Chan