Mstar Semiconductor, Inc.

Kai-Fei Chang

Chun-Chia Chen

Chao-An Chen

Hsian-Feng Liu

Jian-Feng Shiu

Ju-Yu Yu

An LDO with high efficiency receives an input voltage from an input power line and outputs an output voltage at an output power line. The LDO includes a first active device, a second active device, an operational amplifier and a protection circuit. The first and second active devices are connected in series between the input and output power lines via a connecting node. The operational amplifier controls the second active device according to the output voltage and a core power voltage of a core power line to cause the output voltage to stabilize at a target voltage value. The protection circuit is connected to the input and output power lines, the connecting node and a control node of the first active device, and controls a voltage of the connecting node and the control node of the first active device according to the input and output voltages.

LDO with high power conversion efficiency

A receiver includes a control module, a data receiving circuit and a masking circuit. The control circuit generates an enable signal according to a pair of differential signals provided by a transmitter. Triggered by the enable signal, the data receiving circuits generates an output signal according to the differential signals, and the masking circuit starts masking the output signal. After generating the enable signal, the control module starts providing a bias voltage to the differential signals such that the output signal has a first state. The transmitter adjusts the differential signals to render the output signal to enter a second state from the first state. Upon detecting the output signal having entered the second state, the control module stops providing the bias voltage and generates a disable signal to prompt the masking circuit to stop masking the output signal.

Receiver in physical layer of mobile industry processor interface (MIPI-PHY)

A signal transmission method suitable for a signal transmitter includes: providing a plurality of clock signals with different phases, selecting some of the clock signals as a plurality of intermediate signals; transmitting the intermediate signals to a signal output circuit via a clock distribution network; selecting one of the intermediate signals as a reference clock of the signal output circuit to output data.

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Zhubei, Taiwan

Kai-Fei Chang