Taiwan Semiconductor Manufacturing Comp. Ltd.

Kai-Chun Hsu

Shyh-Fann Ting

Ching-Chun Wang

Dun-Nian Yaung

Yeur-Luen Tu

Kuo-Cheng Lee

Chun-Hao Chou

Tzu-Hsuan Hsu

Jeng-Shyan Lin

Chih-Yu Lai

Chun-Wei Chia

Cheng-Hsien Chou

Chun-Wei Chang

Sheng-Chau Chen

Hsiao-Hui Tseng

Shih Pei Chou

Wei-Cheng Hsu

Chia-Shiung Tsai

Jhy-Jyi Sze

Cheng-Ta Wu

Chun-Tsung Kuo

Chung Chien Wang

The present disclosure relates to a semiconductor structure. The semiconductor structure includes a dielectric layer having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall of the dielectric layer. A first conductive layer contacts a bottom surface of the dielectric layer. The sidewall of the dielectric layer is directly over the first conductive layer. A second conductive layer contacts the first conductive layer and the dielectric layer. The second conductive layer vertically extends from the first conductive layer to above the dielectric layer. A third conductive layer contacts the second conductive layer. The third conductive layer is laterally separated from a sidewall of the second conductive layer that faces the third conductive layer by a non-zero distance.

Pad structure for front side illuminated image sensor

An image sensor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a protection oxide film, and a nitride hard mask. The gate dielectric layer is over the semiconductor substrate. The gate electrode is over the gate dielectric layer. An entirety of a first portion of the gate dielectric layer directly under the gate electrode is of uniform thickness. The protection oxide film is in contact with a top surface of the gate electrode. The gate dielectric layer extends beyond a sidewall of the protection oxide film. The nitride hard mask is in contact with a top surface of the protection oxide film.

Image sensor comprising polysilicon gate electrode and nitride hard mask

A method includes depositing a gate dielectric layer over a substrate. A gate electrode layer, a protection oxide layer, and a hard mask are sequentially deposited over the gate dielectric layer. The gate electrode layer and the protection oxide layer are patterned by using the hard mask as an etching mask to form a gate structure over the gate dielectric layer. An etching process is performed to remove the hard mask and thin the protection oxide layer after forming the gate structure.

Method for forming image sensor

The present disclosure relates to an integrated circuit. The integrated circuit includes a plurality of interconnects within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has sidewalls connected to one or more upper surfaces of the passivation structure. A bond pad is arranged directly between the sidewalls of the passivation structure. An upper passivation layer is disposed over the passivation structure and the bond pad. The upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad.

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of interconnect layers within a dielectric structure over an upper surface of a substrate. A passivation structure is formed over the dielectric structure. The passivation structure has sidewalls and a horizontally extending surface defining has a recess within an upper surface of the passivation structure. A bond pad is formed having a lower surface overlying the horizontally extending surface and one or more protrusions extending outward from the lower surface. The one or more protrusions extend through one or more openings within the horizontally extending surface to contact a first one of the plurality of interconnect layers. An upper passivation layer is deposited on sidewalls and an upper surface of the bond pad and on sidewalls and the upper surface of the passivation structure.

An image sensor includes a semiconductor substrate, a gate dielectric layer over the semiconductor substrate, a gate electrode over the gate dielectric layer, and a protection oxide film in contact with a top surface of the gate electrode. A top surface of the protection oxide film is free from contact with a hard mask comprising nitrogen.

Image sensor

The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate.

A method of fabricating polysilicon gate structure in an image sensor device includes depositing a gate dielectric layer on a surface of a substrate. Then a polysilicon layer is deposited over the gate dielectric layer. Next, a protection film is deposited over the polysilicon layer. A hard mask is formed over the protection film, and the polysilicon gate structure is patterned. Following that, the hard mask is stripped off. The protection film exhibits etching selectivity against the polysilicon layer and has a thickness of between 40 and 60 angstroms. The hard mask is removed by phosphoric acid solution wet etching process.

Method of forming polysilicon gate structure in image sensor device

A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes an active area on a substrate, where the active area is at least one of a p-type region or an n-type region. The substrate includes a well, where the well is a p-well when the active area is a p-type region, and the well is an n-well when the active area is an n-type region. The well includes a photodiode. The active area is connected to a voltage supply having a voltage level, such as ground. The active area on the substrate increases a distance between the photodiode and the active area, which reduces junction leakage as compared to a semiconductor arrangement where the active area is formed at least partially within the substrate.

Semiconductor arrangement and formation thereof

A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Method for forming alignment marks and structure of same

A method includes performing a grinding to a backside of a semiconductor substrate, wherein a remaining portion of the semiconductor substrate has a back surface. A treatment is then performed on the back surface using a method selected from the group consisting essentially of a dry treatment and a plasma treatment. Process gases that are used in the treatment include oxygen (O). The plasma treatment is performed without vertical bias in a direction perpendicular to the back surface.

Backside surface treatment of semiconductor chips

Methods are disclosed herein for determining the laser beam size and the scan pattern of laser annealing when fabricating backside illumination (BSI) CMOS image sensors to keep dark-mode stripe patterns corresponding to laser scan boundary effects from occurring within the sensor array regions of the image sensors. Each CMOS image sensor has a sensor array region and a periphery circuit. The methods determines a size of the laser beam from a length of the sensor array region and a length of the periphery circuit so that the laser beam covers an integer number of the sensor array region for at least one alignment of the laser beam on the array of BSI image sensors. The methods further determines a scan pattern so that the boundary of the laser beam does not overlap the sensor array regions during the laser annealing, but only overlaps the periphery circuits.

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Yonghe, Taiwan

Kai-Chun Hsu