International Business Machines Corporation

Kai Cheng

Jin Chin Wang

Kimming K So

Gary Dale Carpenter

Hoichi Cheong

Manuel Joseph Alvarez, Ii

Steven George Aden

Ramanathan Raghavan

Jeffrey Holland Gruger

An apparatus is disclosed which supports memory updates within a data processing system including a number of processors. The apparatus includes a memory hierarchy including one or more upper levels of memory. Each upper level within the memory hierarchy includes one or more memory units which each store a subset of all data stored within an associated memory unit at a lower level of the memory hierarchy. Each memory unit at the highest level within the memory hierarchy is associated with a selected processor. In addition, the apparatus includes a reservation indicator associated with each memory unit within the memory hierarchy. For memory units at the highest level within the memory hierarchy, the reservation indicator specifies an address for which the processor associated with that memory unit holds a reservation. At each lower level within the memory hierarchy, the reservation indicator specifies addresses for which associated memory units at higher levels within the memory hierarchy hold a reservation. A reservation for a selected address within a memory unit is resolved at a highest level within the memory hierarchy at which a memory unit stores data associated with the selected address exclusive of other memory units at that level, thereby enhancing reservation protocol efficiency.

Method and system for memory updates within a multiprocessor data

A method and apparatus in a data processing system having a plurality of node controllers and a memory unit for each of the node controllers. Each one of the node controllers including at least one processor having a cache. Each memory unit including a plurality of entries each having an exclusive bit, an address tag, and an inclusion field. Each bit of the inclusion field representing one of the node controllers. The method and apparatus allow error recovery for errors occurring within the entries without using the ECC implementation. Specifically, two parity bits are used for detecting errors within an entry and logic for flushing any cache lines represented by the entry in error. The method and apparatus also includes means for detecting persistent errors and for indicating whether the error is generated by either hardware or software.

Method and system for implementing parity error recovery schemes in a

A method and system for processing multiple requests for data residing at the same memory address. The multiple requests are associated with an individual duplicate bit flag that indicates whether the request can be processed. Thus, manipulation of the duplicate bit flag controls the order of processing for each of the received requests, thereby maintaining data coherency and integrity.

Method and system for processing multiple requests for data residing at

A system and method for identifying which incoming write data is valid and for insuring that stale data does not overwrite valid data within system memory within a symmetrical multiprocessor data processing system. Upon receipt of a Load Miss request from a processor, a stale bit is established and set equal to zero. A determination is then made of which other processor has ownership of the requested cache line. The requested cache line is then transferred in a cache-to-cache transfer from the second processor to the first processor. If the first processor further modifies the cache line and writes back the cache line to system memory before the original owner of the cache line writes back the stale data with an acknowledgment of the cache-to-cache transfer, the stale bit is set to one. Upon receipt from the acknowledgment from the original owner of the cache line, the stale data is dropped when it is determined that the stale bit has been set.

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Austin, TX, United States of America

Kai Cheng