Intel Corporation

Other

Kai Cheng

Linda J Rankin

James W Alexander

Lily Pao Looi

Nitin Y Borkar

Wen-Hann Wang

Mohan J Kumar

Glenn J Hinton

Debaleena Das

Gilbert A Neiger

David Zimmerman

Rajesh M Sankaran

Robert G Blankenship

Rajat Agarwal

Raj K Ramanujan

Ian M Steiner

Dimitrios Ziakas

Bassam N Coury

Muthukumar Swaminathan

Devadatta V Bodas

Tessil Thomas

Akhilesh Kumar

Bahaa Fahim

Nicholas D Wade

Suresh S Chittor

Son H Lam

Krishnakanth Venkata Sistla

Richard A Uhlig

Rahul Khanna

Avinash N Ananthakrishnan

Yen-Cheng Liu

Sanjay Kumar

Robert J Safranek

Joseph Nuzman

Robert S Chappell

Kenneth C Creta

Paul R Pierce

Gregory E Dermer

Richard H Hofsheier

Faye A Briggs

Manoj Khare

Jeffrey D Gilbert

Camille C Raad

Taarinya Polepeddi

Gopikrishna Jandhyala

Tuan M Quach

Dennis W Brzezinski

Keith Robert Pflederer

Jonathan C Jasper

Meenakshisundaram Chinthamani

David C Lee

Liqun Cheng

Bruce A Christenson

Sambaran Mitra

Ramesh Subashchandrabose

Malcolm Mandviwalla

John A Urbanski

Krishna Kant

Tsvika Kurts

Sailesh Kottapalli

Theodros Yigzaw

Jose Andy Vargas

Julius Yuli Mandelblat

Martin Rowland

Zhong-Ning George Cai

Subramanya R Dulloor

Robin A Steinbrecher

Henk G Neefs

Jiming Sun

Suvansh Krishan Kapur

Saurabh Tiwari

Cesar A Quiroz

Joseph R Doucette

Christian Le

Fernando A Lopez

Celeste M Brown

Robert J Hoogland

Rajat Agrawal

Dableena Das

David J Zimmerman

Jason W Horihan

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as 'far memory.' Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as 'near memory.'

Apparatus and method for implementing a multi-level memory hierarchy

An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.

Method and apparatus for store durability and ordering in a persistent memory architecture

Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

Method and apparatus for injecting errors into memory

Methods, techniques, systems and apparatuses for utilizing reserved space for error correcting functionality. A cache line ('reserved line') in a plurality of cache lines to store error correcting code (ECC) data is utilized for storing ECC data corresponding to other cache lines within the plurality of cache lines when a memory device has failed.

Error correcting code scheme utilizing reserved space

A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.

Mechanism for achieving high memory reliability, availability and serviceability

An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.

Method, apparatus, and system for energy efficiency and energy conservation including dynamic control of energy consumption in power domains

Mechanism for achieving high memory reliablity, availability and serviceability

Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Rank-specific cyclic redundancy check

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Scalable distributed memory and I/O multiprocessor system

The storage locations of a snoop filter are segregated into a number of groups, and some groups are associated with some processors in a system. When new data enter a cache line of a processor, one of the storage locations associated with the processor is selected for further operations.

Pseudo least recently used replacement/allocation scheme in request agent affinitive set-associative snoop filter

Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.

Systems, methods and apparatuses for clock enable (CKE) coordination

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BICS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

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Portland, OR, United States of America

Kai Cheng