Xilinx, Inc.

Realtek Semiconductor Inc.

Kai-An Hsieh

Tan Kee Hian

Kevin Zheng

Yi-Chun Hsieh

A digital-to-analog converter (DAC)-based voltage-mode transmit driver architecture. One example transmit driver circuit generally includes an impedance control circuit coupled to a plurality of DAC driver slices. The impedance control circuit generally includes a tunable impedance configured to be adjusted to match a load impedance for the transmit driver circuit. Another example transmit driver circuit generally has an output impedance that is smaller than the load impedance for the transmit driver circuit, such that an output voltage swing at differential output nodes of the transmit driver circuit is greater than a voltage of a power supply rail. Another example transmit driver circuit generally includes a predriver circuit with a first inverter coupled to a first output of the predriver circuit and a second inverter coupled to a second output of the predriver circuit, the transistors in at least one of the first inverter or the second inverter having different strengths.

Digital-to-analog converter (DAC)-based voltage-mode transmit driver architecture with tunable impedance control and transition glitch reduction techniques

Analog-to-digital converter circuitry includes comparator circuitry, capacitor analog-to-digital converter circuitry (CDA), and successive approximation register (SAR) circuitry. The comparator circuitry includes a non-inverting input and an inverting input to selectively receive a differential voltage signal, and an output. The CDAC circuitry includes a first capacitor network having a first plurality of capacitors. A first capacitor of the first plurality of capacitors includes a first terminal connected to the non-inverting input and a second terminal selectively connected to a first voltage potential and a second voltage potential. The first voltage potential is greater than the second voltage potential. The SAR circuitry is connected to the output and the first capacitor network, and connects, during a first period, the second terminal of the first capacitor to the second voltage potential. The non-inverting input and the inverting input are connected to the differential voltage signal during the first period.

Offset mitigation for an analog-to-digital convertor

Embodiments herein describe placing a filter network at one of the inputs of the comparator to avoid injecting unequal amounts of kickback noise into the inputs of the comparator. In one embodiment, the filter network matches the impedance seen at the inputs of the comparator. As a result, the amount of kickback noise is essentially equal at the inputs even though the input signals may be at different frequencies. Thus, the kickback noise is essentially cancelled out so that this noise has little to no impact on the output of the comparator.

Mitigating the effects of kickback noise on a comparator

A communication apparatus includes an input terminal, an output terminal, and an interference reduction circuit. The interference reduction circuit is coupled between the input terminal and the output terminal. The interference reduction circuit receives a time-varying data signal. The interference reduction circuit acquires first partial data from the data signal at a first time, and generates a first level-shifted result and a second level-shifted result according to the first partial data. The interference reduction circuit is further configured to acquire second partial data from the data signal at a second time. The interference reduction circuit selects one of the first level-shifted result and the second level-shifted result as a selected result according to the second partial data, and sends the selected result to the output terminal.

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Tainan, Taiwan

Kai-An Hsieh