International Business Machines Corporation

Globalfoundries Inc.

Kahn C Evans

Alan G Gara

David L Satterfield

Kristan D Davis

Michael K Gschwind

Valentina Salapura

Dong Chen

Paul William Coteus

Matthew Stephen Doyle

Michael A Blocksome

Joseph D Ratterman

Philip Heidelberger

Adam James Muff

Todd Edward Takken

Martin Ohmacht

Bruce Martin Fleischer

Alexandre E Eichenberger

Thomas M Gooding

Robert William Wisniewski

John A Gunnels

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Kathryn Mary O'Brien

Mark Gregory Megerian

Sameh W Asaad

Matthias Augustin Blumrich

Shawn Anthony Hall

John Kevin O'Brien

Thomas Winters Fox

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Charles David Wait

Sameer Kumar

James Anthony Marcella

George L Chiu

Todd Alan Inglett

Krishnan Sugavanam

Christopher John Engel

Gerard Vincent Kopcsay

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

Douglas R Miller

Craig Brian Stunkel

Rudolf Adriaan Haring

Yutaka Sugawara

Amith R Mamidala

Jose R Brunheroto

Michael B Mundy

Matthew Roger Ellavsky

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Gabor J Dozsa

Ruth Janine Poole

Ralph E Bellofatto

Peter Boyle

Brant L Knudson

Norman Christ

Jason T Albert

William Maupin Stockdell

Alfred Thomas Watson, Iii

Steven B Janssen

Matt K Light

Brian E Smith

A method of probing printed circuit boards that includes providing a circuit board design including a plurality of probe points, and selecting a probe point including a location ink from the plurality of probe points in the circuit board design to be probed on a physical printed circuit board design. The method continues with probing at least one probe point of the plurality of probe points with a probe that activates the location ink. Activation of the location ink by the probe indicates the selected probe point including the locating ink.

Method for identification of proper probe placement on printed circuit board

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.

Distributed performance counters

Growing community of inventors

Rochester, MN, United States of America

Kahn C Evans