International Business Machines Corporation

Kafai Lai

Alan Edward Rosenbluth

Maharaj Mukherjee

Gregg M Gallatin

Mark Alan Lavin

Shlomo Shlafman

Dov Ramm

Emanuel Gofman

Michael A Guillorn

Hsinyu Tsai

Chi-Chun Liu

Rasit Onur Topaloglu

Joy Cheng

Kehan Tian

Jed Walter Pitera

Saeed Reza Bagheri

Wai-Kin Li

Damon B Farmer

Charles Thomas Rettner

Abram L Falk

David Osmond Melville

Dirk Pfeiffer

Daniel Sanders

Young-Hye Na

Rama Nand Singh

Jessie Carrigan Rosenberg

Ananthan Raghunathan

Rajasekhar Venigalla

Dongbing Shao

Cheng Chi

Da Yang

Chih-Chao Yang

Rajiv V Joshi

Zheng Xu

Ping-Chuan Wang

Reinaldo Ariel Vega

Hsueh-Chung Chen

Kai D Feng

Hiroyuki Miyazoe

Albert Manhee Chu

Dario Leonardo Goldfarb

Raschid Jose Bezama

Sean David Burns

Yongan Xu

Timothy A Brunner

Fook-Luen Heng

Zhijian Yang

Jaione Tirapu Azpiroz

Scott Marshall Mansfield

Ioana C Graur

Hari V Mallela

David O S Melville

Dmitriy Shneyder

Saibal Mukhopadhyay

Gregory S Doerk

Lin Hu

Melih Ozlem

Lawrence Alfred Clevenger

Guy M Cohen

Sivananda K Kanakasabapathy

Sharathchandra UmapathiRao Pankanti

Su Chen Fan

Ravikumar Ramachandran

Wu-Song S Huang

Xiao Hu Liu

Markus Brink

James A Culp

Huan Hu

Kuang-Jung Chen

Ankit Vora

Daniel James Dechene

Jing Sha

Scott Josef Bukofsky

Carlos A Fonseca

Alan C Thomas

Kristin Schmidt

Bernhard R Liegl

Chieh-Yu Lin

Nakgeuon Seong

Ronald L Gordon

Zheng G Chen

Jaione Tirapu-Azpiroz

Rasit Onur Topalogu

Nayak Jawahar

Daniel Paul Sanders

Wai-Kim c/o Ibm United Kingdom Limited Li

A semiconductor structure comprises a substrate, a patch of optically tunable material disposed over the substrate, a first electrode coupled to the patch of optically tunable material and a switch providing a current source, and a second electrode coupled to the patch of optically tunable material and a ground voltage. The first electrode and the second electrode are configured to modify a state of the patch of optically tunable material to adjust a reflectivity of the patch of optically tunable material.

Reconfigurable geometric metasurfaces with optically tunable materials

A tunable metasurface is provided. The tunable metasurface includes a mirror, a dielectric layer disposed on the mirror, a metallic antenna and a phase change material (PCM) layer. The PCM layer is interposed between the dielectric layer and the metallic antenna. The PCM layer is configured to be amorphous or crystalline. The mirror, the dielectric layer, the metallic antenna and the PCM layer cooperatively form a Fabry Perot cavity in which light incident on the metallic antenna from free space is reflected between the mirror and the metallic antenna. The PCM layer has blanket dimensions relative to those of the metallic antenna such that the Fabry Perot cavity is critically coupled with the free space when the PCM layer is only one of amorphous and crystalline.

Configurable geometric metasurface antenna

A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

Self-aligned double patterning with spacer-merge region

A method, apparatus and computer program product for using a volumetric CAPTCHA display to verify that a human is present at a computer. Responsive to a request for a computer resource, a volumetric CAPTCHA is displayed in a user interface at the computer. The volumetric CAPTCHA has a first three dimensional (3D) feature and a second 3D feature. The user is prompted to answer a question about the first 3D feature of the volumetric CAPTCHA display. The received user response to the question is evaluated for correctness in describing the first 3D feature of the volumetric CAPTCHA. In response to the received user response being correct, the user is allowed access to the computer resource. The first 3D feature and the second 3D feature have a relationship with each other in the volumetric CAPTCHA.

Volumetric display-based CAPTCHA system

An apparatus includes two or more electrically rotatable antennas providing a reconfigurable metasurface, each of the electrically rotatable antennas including a disk of optically tunable material. The apparatus also includes a control circuit including a plurality of switches each coupled to (i) one of a plurality of electrodes, the plurality of electrodes being arranged proximate different portions of at least one surface of each of the disks of optically tunable material and (ii) to at least one of a current source and a ground voltage. The control circuit is configured to modify states of portions of the optically tunable material in each of the disks of optically tunable material utilizing current supplied between at least two of the plurality of electrodes to adjust reflectivity of the portions of the optically tunable material to dynamically reconfigure respective antenna shape configurations of each of the electrically rotatable antennas.

Electrically rotatable antennas formed from an optically tunable material

An apparatus includes two or more tunable antennas providing a reconfigurable metasurface, each of the tunable antennas including a plurality of pixels of optically tunable material, and a control circuit including switches providing current sources and a ground voltage, the switches being coupled to respective ones of the pixels of optically tunable material in each of the tunable antennas via first electrodes, the ground voltage being coupled to respective ones of the pixels of optically tunable material in each of the tunable antennas via second electrodes. The control circuit is configured to modify states of respective ones of the plurality of pixels of optically tunable material in the tunable antennas utilizing current supplied between the first electrodes and the second electrodes to adjust reflectivity of the plurality of pixels of optically tunable material in each of the tunable antennas to dynamically reconfigure respective antenna shape configurations of the tunable antennas.

Reconfigurable metasurface with tunable antennas formed from arrays of pixels of an optically tunable material

An apparatus includes two or more groups of antennas, each including two or more patches of optically tunable material providing two or more antennas. The tunable geometric metasurface also includes a control circuit including a plurality of switches providing current sources and a ground voltage. The plurality of switches are coupled to respective ones of the patches of optically tunable material in each of the groups of antennas via first electrodes. The ground voltage is coupled to respective ones of the patches of optically tunable material in each of the groups of antennas via second electrodes. The control circuit is configured to modify states of the antennas in each of the groups of antennas utilizing the first electrodes and the second electrodes to adjust reflectivity of the patches of optically tunable material to provide a tunable geometric metasurface.

A semiconductor structure includes a substrate and a first trench including a dielectric material disposed in the substrate. The first trench includes a transferred pattern of a first polymer of a directed self-assembly stack including the first polymer and a second polymer. The semiconductor structure also includes a second trench including a first vertical metal plate disposed in the substrate adjacent a first sidewall of the first trench, and a third trench including a second vertical metal plate disposed in the substrate adjacent a second sidewall of the first trench. The first vertical metal plate in the second trench, the dielectric material in the first trench, and the second vertical metal plate in the third trench provide a metal-insulator-metal vertical plate capacitor.

Vertical plate capacitors exhibiting high capacitance manufactured with directed self-assembly

A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising expanding a shape of the guiding pattern by a predetermined distance in both lateral directions to form a fin keep mask, where the fin keep mask comprises a stand-alone mask.

Reducing chemoepitaxy directed self-assembled defects

Verifying a product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the product.

Integrated circuit security

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate cut mask having one cut window exposing one or more portions of multiple sacrificial gate structures of the at least one plurality of sacrificial gate structures. The multiple sacrificial gate structures having been formed over portions of in structures. The method comprises forming a gate cut mask a plurality of semiconductor fins and a plurality of sacrificial gate structures. The gate cut mask being formed with one cut window exposing one or more portions of multiple sacrificial gate structures of the plurality of sacrificial gate structures. At least the portion of multiple sacrificial gate structures and one or more portions of each semiconductor fin of the plurality of semiconductor fins underlying the one or more portions of one of the multiple sacrificial gate structures are removed.

Fabricating tapered semiconductor devices

Various semiconductor fabrication methods and structures are disclosed for cost effectively fabricating a self-aligned contact. A source-drain active region is on a substrate and horizontally extends to sidewall spacers of two adjacent gate stacks on the substrate. A conductive material layer including Titanium is formed by selective deposition on the source-drain active area. An interlevel dielectric (ILD) layer is deposited over the source-drain active area and the two gate stacks. Vertical directional etching in the ILD layer forms a vertical trench contacting the conductive material layer. Selective wet etching in the vertical trench selectively etches the conductive material layer and forms a void therein. Deposition of a second conductive material in the vertical trench fills the vertical trench, including the void, and the second conductive material contacts the top surface of the source-drain active area to form a source-drain self-aligned contact.

Method and structure for cost effective enhanced self-aligned contacts

Methods and systems for generating a random number include extracting feature information from a structure having a random physical configuration. The feature information is converted to a string of binary values to generate a random number. Pseudo-random numbers are generated using the random number as a seed to improve the security of encrypted information.

Self-assembly based random number generator

Multi-patterning methods are provided for use in fabricating an array of metal lines comprising metal lines with different widths. For example, patterning methods implement spacer-is-dielectric (SID)-based self-aligned double patterning (SADP) methods for fabricating an array of metal lines comprising elongated metal lines with different widths, wherein an 'unblock' mask is utilized as part of the process flow to overlap mandrel assigned and non-mandrel assigned features in a given SADP pattern to define regions to unblock a metal fill (remove dielectric material between wires) in a dielectric layer between defined metal lines of an a SADP pattern thus enabling the formation of wide metal lines within any region of a pattern of elongated metal lines formed with a minimum feature width.

Multi-patterning techniques for fabricating an array of metal lines with different widths

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Poughkeepsie, NY, United States of America

Kafai Lai