Infineon Technologies Ag

Infineon Technologies Austria Ag

Kae-Horng Wang

Francisco Javier Santos Rodriguez

Michael Knabl

Guenther Koffler

Martin Mischitz

Elard Stein Von Kamienski

Matthias Kroenke

Matthias Krönke

John Cooper

Ralf Staub

Wolfgang Gustin

Klaus Feldner

Karl Heinz Gasser

Grit Schwalbe

Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.

Metal deposition on substrates

Methods, apparatuses and devices relate to inkjet printing a covering layer on at least a first side of a substrate in a peripheral region thereof are discussed.

Inkjet printing in a peripheral region of a substrate

One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines. The semiconductor component is fabricated in the following way: application of a polysilicon layer to the semiconductor wafer, patterning of the polysilicon layer, in order to produce a polysilicon contact above the active area, the polysilicon contact at least partly covering the two control lines, application of a first insulator layer to the semiconductor wafer, with the polysilicon contact being embedded, partial removal of the first insulator layer, so that at least the upper surface of the polysilicon contact is uncovered, and application of a metal layer to the semiconductor wafer in order to make electrical contact with the polysilicon contact.

Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts

A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells disposed at the points at which the bitlines and wordlines cross each other. According to a first aspect of the present invention, the isolating layer is removed from the bitlines at the portions that are not covered by the wordlines, whereas the areas between the bitlines remain unaffected. Alternatively, the isolating layer is removed from the whole cell array. Then, an electrical conductive material is provided on the exposed portions of the bitlines. The method is used to provide bitline contacts in a nitride read only memory (NROM&#x2122;) chip.

Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts

The invention relates to a method for the production of an integrated circuit, comprising the following steps: a substrate () is provided with at least one first, second and third gate stack (GS, GS, GS) of approximately the same height surface of said substrate, a common active area () being provided on the surface of the substrate in said substrate () between the first and second gate stack (GS, GS); a first insulating layer () is provided in order to cover the embedding of the first second and third gate stack (GS, GS, GS); the upper side of a gate connection () of the third gate stack (GS) is uncovered; a second insulating layer () is provided in order to cover the upper side of a gate connection (); a mask (M) is provided on the resulting structure having a first opening () above the uncovered upper side of the gate connection () of the third gate stack (GS), a second opening (F) above the substrate () between the third and second gate stack (GS, GS) and a third opening (F) above the common active area (), partially overlapping the first and second gate stack (GS, GS), and simultaneously forming a first, second and third contact hole (KB, KS, KG) using said mask () in an etching process, the first contact hole (KB) uncovering the common active area () on the surface of the substrate between the first and second gate stack (GS, GS), the second contact hole (KS) uncovering the surface of the substrate between the second and third gate stack (GS, GS) and the third contact hole (KG) uncovering the upper side of the gate connection () of the third gate stack (GS).

Method for the production of an integrated circuit

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Villach, Austria

Kae-Horng Wang