Digital Equipment Corporation

Cabletron Systems, Inc.

Other

Compaq Computer Corporation, Inc.

Enterasys Networks, Inc.

Kadangode K Ramakrishnan

Michael Ben-Nun

Henry S Yang

Peter J Roman

Anthony G Lauck

Simoni Ben-Michael

Anna Charny

William R Hawe

G Paul Koning

Lev Vaitzblit

Prabuddha Biswas

Moshe De-Leon

Percy Tzelnic

Dennis P Ting

Satish L Rege

Douglas M Washabaugh

Frank A Itkowsky

Stanley Chmielecki

David A Gagne

Paul W Ciarfella

Aviad Wertheimer

David S Sawyer

Phillip J Weeks

Gady Daniely

Simcha Perl

Bhupendra Shah

Douglas M Washbaugh

A rate based, end to end flow control system is disclosed for a communications network. The disclosed rate based flow control system includes each source end station selecting its transmission rate from a set of permitted discrete transmission rates. The set of permitted discrete transmission rates is based on a logarithmic encoding. The disclosed rate based traffic control system further requires each source end station to send one end to end control cell every time period T. The time period T is also known by switches in the communications network and is used to periodically calculate an available allocation (&ldquo;fair share&rdquo;) of bandwidth at a switch for a given virtual circuit.

Traffic control system having distributed rate calculation and link flow control

In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further than notification of non-error and maintenance status changes are processed with minimal latency.

Arbitration system based on requester class and relative priority including transmit descriptor valid bit for a shared resource having multiple requesters

Method and apparatus for avoiding receive livelock and transmit starvation, and for minimizing packet loss and latency in a communication network station. The invention uses a combination of processing threads, polling and, in a preferred embodiment, a judicious use of interrupts, to allocate the use of processing resources fairly among competing functions. Real time processing threads are structured to execute for a preselected maximum time interval, based on numbers of units processed by each thread, and then to yield control to a thread scheduler, which selects and invokes a new thread for execution. Work to be done in the various threads is determined either by polling or by an interrupt system, and then posted to the threads for execution. If interrupts are used, interrupt service routines perform only the minimal processing needed to recognize an interrupt, other interrupt servicing functions being deferred for execution in a processing thread. The thread scheduler operates on a round-robin basis and also selects from at least one general purpose processing thread for functions that are less time critical, the general purpose thread being structured to operate for a selected minimum time, if needed, in a non-preemptable mode, and thereafter in a preemptable mode.

Scheduling mechanism using predetermined limited execution time

The rate based end system may provide feasible transmission rates for end source stations. As an extension to the rate based end to end system, there is disclosed a hybrid link by link flow control system. The link by link control system is built upon the end to end, rate based traffic control system. The link by link system utilizes bandwidth un accounted for by the end to end system. The link by link system uses feasible transmission rates obtained by the end to end system to determine the size of the buffers required for overbooking and for updating credit information to sustain the calculated rate.

Traffic control system having distributed rate calculation and link by

In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further that notification of non-error and maintenance status changes are processed with minimal latency.

Arbitration system based on requester class and relative priority

Arbitration system for a shared DMA logic on a network adapter with a

In an asynchronous transfer network (ATM), to prevent the bottleneck associated with a host central processing unit (CPU) trying to receive status information for a plurality of interrupts occurring over an interface input/output (I/O) bus, a method and apparatus which transfers all status information directly to the host memory without host involvement. The host CPU is then notified of this new status information via an interrupt. When status information is transferred to the host memory, consistency is ensured and the number of spurious interrupts are reduced. A host software driver may then read the latest status information from the interface I/O bus at its convenience any not incur any performance penalties of I/O accesses.

Method and apparatus for updating host memory in an adapter to minimize

An apparatus and method for transferring data in a data processing system to and from a host system. A communication adapter or input/output controller device is provided in which queues are utilized to transfer information between the adapter or controller and the host system. In order to minimize the amount of time a system or I/O bus or network is used during transfer of data between the adapter or controller and the host system, and reduce the amount of work that must be performed by the host system, the number of interrupts by the adapter or controller of the host system is limited to the minimum amount necessary by using an interrupt arm mechanism and by keeping track of completion indices stored in the host system.

Apparatus and method for controlling interrupts to a host during data

A rate based, end to end flow control system is disclosed for a communications network. The disclosed rate based flow control system includes each source end station selecting its transmission rate from a set of permitted discrete transmission rates. The set of permitted discrete transmission rates is based on a logarithmic encoding. The disclosed rate based traffic control system further requires each source end station to send one end to end control cell every time period T. The time period T is also known by switches in the communications network, and is used to periodically calculate an available allocation (or 'fair share') of bandwidth at a switch for a given virtual circuit.

A technique for modifying the IEEE 802.3 standard for selecting backoff times in a Carrier Sense Multiple Access with Collision Detection (CSMA/CD) network, in the event that a collision is sensed by a node that has captured the network communication channel. If there is a small number of active nodes on the network, one node may capture the channel and the standard backoff algorithm makes it increasingly unlikely for another node to transmit. The new technique provides for less aggressive, i.e. longer, backoff times before at least the first retransmission attempt made by a node that has captured the channel. Three specific examples of the technique are disclosed. Even though the invention represents a departure from the standard CSMA/CD backoff algorithm, the overall average backoff times provided by the invention can be selected to be consistent with the average times provided by the standard. Moreover, nodes using the invention interoperate successfully with nodes that do not.

Method and apparatus for use in a network of the ethernet type, to

A system for controlling the transmission of cells from a network node over multiple virtual circuit is disclosed. The disclosed system performs traffic shaping for all virtual circuits connected with the network node. The system includes a virtual circuit table with one or more entries. Each virtual circuit table entry corresponds to a virtual circuit established with the network node. Each virtual circuit table further includes one or more Cell Rate Accumulator fields and a Time Stamp field. The system includes a schedule table having one or more entries. Each schedule table entry further includes one or more Cell Rate Accumulator fields and corresponding predetermined value fields. A schedule table loading process determines a virtual circuit on which a packet is to be transmitted, and then calculates a time elapsed since a last previous write of a virtual circuit table entry corresponding with that virtual circuit. The schedule table loading process then adds the time elapsed to the value of the Cell Rate Accumulator fields in that virtual circuit table entry, and stores the result of the addition into the corresponding Cell Rate Accumulator fields of the schedule table entry. The system further includes a process for periodically incrementing the Cell Rate Accumulator fields in the schedule table entry. A scanning process periodically increments the Cell Rate Accumulator fields. A transmitting process transmits a cell on the virtual circuit when the value of the Cell Rate Accumulator fields is greater than or equal to the corresponding predetermined values.

Traffic shaping system with virtual circuit table time stamps for

A method, and apparatus for its use, for reducing the number of disk accesses needed to satisfy requests for reading data from and writing data to a hard disk. A non-volatile cache memory used to hold data blocks for which write requests have been made is purged of 'dirty' blocks, not yet written to the disk, based on the proportion of dirty blocks in relation to an upper threshold and a lower threshold. A purge request flag is set when the proportion of dirty blocks goes above the upper threshold, but is not cleared until the proportion of dirty blocks goes below the lower threshold. So long as the purge request flag is set, dirty blocks are purged when the disk is not busy with read requests. Immediate purging is initiated when the write cache becomes totally full of dirty blocks. Purging of dirty blocks is also effected during disk read accesses, by 'piggybacking' a writing operation with the reading operation, to write dirty blocks destined for the same track or cylinder in which the requested read data blocks are located.

Disk cache management techniques using non-volatile storage

An Asynchronous Transfer Mode (ATM) network device having a receiver portion capable of receiving ATM cells on one of a number of virtual circuits (VCs) from an upstream ATM switch, a local memory used to store the ATM cells, a management system to manage the local memory using a number of queues, a system for assembling ATM cells into packets, a system for transmitting the packets to a host memory, and a transmitter portion having a system for indicating the transmitting of packets to the host memory to the upstream ATM switch.

Local memory buffers management for an ATM adapter implementing credit

An arbiter of an I/O controller implements an arbitration process for controlling bi-directional data flow between a local area network and a main memory connected to a system bus having variable latency. A receive state machine of the controller manages inbound data bursts from the network by temporarily storing the data in a receive buffer before transfer to the main memory. Outbound data bursts from the main memory are managed by a transmit state machine of the controller, and are temporarily stored in a transmit buffer prior to transmission onto the network. The arbitration process assigns each of the receive and transmit state machines priority for accessing the system bus depending upon certain status conditions of the controller. These conditions include: (i) whether one or both of the state machines are contending for access to the system bus; (ii) whether the controller is configured for full-duplex or half-duplex communication over the network; (iii) the current status of the transmit and receive network ports; and (iv) the current state of the receive and transmit buffers.

Method for assigning priority to receive and transmit requests in

A scheduler with admissions control in a continuous media file server is presented. The scheduler supports multiple classes of tasks with diverse performance requirements. The scheduler is based on a combination of rate-monotonic and weighted round-robin scheduling schemes. Scheduling is accomplished in a hierarchical manner. Isochronous tasks have the highest priority and are scheduled first followed by real-time and general-purpose tasks. Isochronous tasks run periodically and are invoked by a timer interrupt set for each task. After scheduling the isochronous tasks, the scheduler alternates between the real-time tasks and the general-purpose tasks using a weighted round-robin scheme.

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Maynard, MA, United States of America

Kadangode K Ramakrishnan