Lucent Technologies Inc.

Kadaba R Lakshmikumar

Krishnaswamy Nagaraj

Khong-Meng Tham

Angelo Rocco Mastrocola

David Arthur Rich

Mirmira Ramarao Dwarakanath

Douglas Edward Sherry

A method and apparatus for changing the open-loop frequency response of an amplifier in a line driver when the load to the line driver is removed. The load is detected by measuring the current to the load. When the current falls below a predetermined amount, the load is assumed to be disconnected and the open-loop frequency response of the amplifier is changed to shift a dominant pole of the line driver to a sufficiently low frequency to ensure stability of the line driver.

Load termination sensing circuit

A system for aligning the phase of signals generated by a selectable standby clock source which has a predetermined frequency with the phase of signals generated by a selected clock source which has the same frequency as signals generated by the standby clock source. The system comprises (1) a delay line having a plurality of delay elements which is configured to receive the signals generated by the standby clock source so that the output signal of each delay element is a delayed version of the standby clock source; (2) a decoder configured to receive each of the delayed versions of the signals generated by the standby clock signal source and generates a selection signal corresponding to a desired one of the delayed version signals that is aligned with signals generated by the selected clock source within a specifiable phase difference; and (3) a selector configured to receive the selection signal so as to select the desired delayed version signal as a new standby clock source.

Phase aligner system and method

A frequency synthesizer is supplied with an input signal of frequency .function..sub.i to provide an output signal .function..sub.o where .function..sub.o=.function..sub.i M/N and M and N are integers. The input signal is first applied to a divider circuit for division by M/K where K is an integer and the resultant is applied as inputs to a phase locked loop. The phase locked loop includes a ring oscillator of frequency .function..sub.i N/M, a frequency multiplier circuit for multiplying by K, and a frequency divider circuit for dividing by N. The ring oscillator uses a combinational logic circuit that combines the outputs of four differential delay elements to produce a frequency multiplication of four.

PLL frequency synthesizer with K multiplication in addition to division

A receiver for decoding passband signal pulses transmitted in accordance with a M-ARY phase shift keying modulation scheme, comprises a multiphase sampler for sampling received passband signal pulses in the passband frequency range so as to generate a plurality of digital words corresponding to the sampled passband signal pulses, such that each digital word represents the phase of each sampled passband signal pulse. A phase reference register or other storage device is coupled to the multiphase sampler for storing one of the digital words as a phase reference such that other digital words generated by the multiphase sampler are compared with the digital word corresponding to the phase reference for decoding the passband signal pulses.

MPSK demodulator

A rail-to-rail voltage-to-current converter converts a variable differential voltage signal having first and second voltage signal components, to an output current signal. The converter includes a first voltage-to-current converter configured to receive a voltage signal component and a reference voltage signal to provide a substantially linear output current signal. A second voltage-to-current converter receives the other one of the voltage signal components and the reference voltage signal to provide a second substantially linear output current signal. An adder combines the first and second output current signals to provide a substantially linear voltage/current characteristic over a wide range of available voltage signals generated by a power supply.

Voltage-to-current converter

A digital phase detector which generates low jitter when the phase-locked-loop is in lock. A delay line, combined with an UP/DOWN phase detector causes substantial overlap in the UP and DOWN signals from the detector. When the PLL is in lock, the overlapping signals substantially cancel each other out, minimizing the variations in the output frequency. Two approaches are disclosed: one delaying the UP signal sufficiently to overlap the DOWN signal, the other using a delay and an exclusive OR gate to generate the DOWN signal.

Low jitter phase detector for phase locked loops

Briefly, in accordance with one embodiment of the invention, a charge pump comprises: a plurality of transistors coupled in a transistor circuit configuration. The transistor circuit configuration is adapted to be coupled to an electronic circuit. The plurality of transistors are coupled so as to deliver electrical charge to the electronic circuit in response to applied signals as the difference of two substantially predetermined currents.

Charge pump having high switching speed and low switching noise

Briefly, in accordance with one embodiment of the invention, a current source comprises: a first and a second current path, the current paths being coupled so as to provide, during circuit operation, first and second currents through the respective current paths in a substantially predetermined direct proportion. The current source further includes an operational amplifier having its respective input terminals coupled to the first and second current paths, the operational amplifier being coupled in a feedback configuration so as to maintain substantially equal voltages between a first and second predetermined point respectively located along the first and second current paths. Furthermore, the respective first and second currents are related to the respective first and second voltages substantially in accordance with the junction diode equation.

PTAT current source

A line driver having two halves arranged in a push-pull configuration. Each half has a pass transistor, connected between a power supply rail and an output terminal, and an amplifier with an output coupled to the output terminal. Only one of the pass transistors conducts at any given time. A sense transistor, coupled between the power supply rail and the input of the amplifier, varies the output of the amplifier to compensate for variations in the conductivity of the conducting pass transistor. Preferably, the current density in the sense transistor is substantially the same as in the conducting pass transistor.

Voltage signal line driver comprising a push-pull bridge amplifier

Briefly in accordance with one aspect of the present invention, a voltage-to-current converter for converting an input voltage signal to an output current signal, exhibits a substantially linear voltage/current characteristics over the entire available voltage signal range. The voltage-to-current converter comprises a first voltage-to-current converter having a substantially linear voltage/current characteristic for input voltage signals smaller than a first reference voltage signal level and up to substantially the minimum voltage signal level generated by a DC power supply employed to drive the voltage-to-current converter. A second voltage-to-current converter has a substantially linear voltage/current characteristic for voltage input signals larger than a second reference voltage signal level and up to substantially the maximum voltage signal level generated by the DC power supply. A control circuit is coupled to activate the first voltage-to-current converter, when the input voltage signal is smaller than the first reference voltage signal, and to activate the second voltage-to-current converter when the input voltage signal is larger than the second reference voltage signal level.

In a ring oscillator, a delay unit includes an input stage having a first and a second input port and a first and a second differential output port. At least two delay units are coupled together so as to form the ring oscillator. The delay unit further includes a first capacitor coupled to the first differential output port of each one of the delay units and a second capacitor is coupled to the second differential output port of the delay unit. A switching accelerator is coupled to the first and second capacitors so as to reduce the time it takes to switch between charged and discharged states for the capacitors. In accordance with another aspect of the invention, a method for providing a delay in a delay unit, the delay of the delay unit being dependent, at least in part, upon the time to charge and discharge a capacitor coupled in the delay unit, the method including the steps of: providing a current signal to the delay unit in a manner so as to cause the capacitor to enter a charged state from a prior discharged state; and accelerating the switching between the discharged and charged states so as to reduce the time it takes to switch between the discharged and charged states for the capacitor.

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Wescosville, PA, United States of America

Kadaba R Lakshmikumar