Samsung Electronics Co., Ltd.

Kab Ju Moon

Amjad Z Qureshi

Le Trong Nguyen

Hoyoung Kim

A DMA controller has a first data buffer and a second data buffer. First data from a first bus can be loaded into the first data buffer at the same time that second data from a second bus is loaded into the second data buffer. Once the data is present in the first and second data buffers, the first data in the first data buffer can be supplied to the second bus at the same time that the second data in the second data buffer is supplied to the first bus (or alternatively to a third bus). In some embodiments, the second bus is a high speed parallel bus and the first and third data buses are I/O data buses for coupling the DMA controller to codecs. In some embodiments, data from the first data bus can be loaded into the first data buffer at the same time that data in the second data buffer is supplied to the third data bus. An address generator generates addresses onto the second data bus for the transfer of data between the DMA controller and the second data bus.

Simultaneous data transfer through read and write buffers of a DMA

A DMA controller receives size data in association with a DMA request. If first size data is received, a first amount of data (for example, one word) is transferred through the DMA controller for the DMA request. If, on the other hand, second size data is received, then a second amount of data (for example, two words) is transferred through the DMA controller for the DMA request. In the event that a DMA request cannot be serviced when received, the DMA request is stored in the DMA controller for later servicing. Size data for a DMA request is stored so that the size of the data transfer will be known when the stored DMA request is serviced. Using this size data, a single DMA channel can support data transfers of different sizes. In some embodiments, size data is used to increment a DMA current address register by the correct amount after the data associated with the size data is transferred through the DMA controller.

DMA controller which receives size data for each DMA channel

A DMA controller receives a DMA request from a DMA channel and generates a transaction request ID identifying the requested transaction as well as a codec ID identifying the DMA channel. The codec ID is stored in the DMA controller in association with the transaction request ID. The DMA controller obtains control of the bus and outputs a transaction request onto the bus along with the transaction request ID. The DMA controller then relinquishes control of the bus. A device on the bus returns the transaction request ID when it responds (the transaction request ID is 'tagged' to the response). The DMA controller uses the returned transaction request ID to look up the codec ID stored in the DMA controller in association with that transaction request ID. The DMA controller uses the codec ID to associate the response with the correct DMA channel. In the event the split transaction is a posted read, the DMA controller uses the returned transaction request ID to supply the data to the DMA channel that issued the DMA request.

DMA controller with channel tagging

An SDRAM initialization and power on system includes a configuration validation circuit for registers in a Memory Controller Unit and a Power On Sequence State Machine. The validation circuit asserts a status signal Config.sub.-- OK if the configuration of the memory control unit is correct. The signal Config.sub.-- OK enables the Power On Sequence State Machine. A status signal PowerOn.sub.-- OK is asserted once the SDRAMs have been initialized. The SDRAMs are not accessible for normal operation unless Config.sub.-- OK and PowerOn.sub.-- OK are asserted. By monitoring the two signals Config.sub.-- OK and PowerOn.sub.-- OK, debugging can be much more efficient and corruption of SDRAMs with bad data can be avoided.

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Cupertino, CA, United States of America

Kab Ju Moon