Solomon Systech Limited

Ka Wai Cheung

Yin Yan Li

Wai Hon Ng

Chi Wai Lee

The integrated circuit memory comprises a memory array including a plurality of memory cells in rows and columns, the memory array being divided into a plurality of blocks of the memory cells. Each of the blocks includes a plurality of word lines arranged along the rows and coupled to the memory cells, a plurality of first and second bit lines alternately allocated along every other column, a first selecting line for providing a control signal, a second selecting line for providing the control signal, a plurality of first selecting transistors having their gates coupled to the first selecting line to receive the control signal, each of the first selecting transistors for coupling one of the memory cells in a selected row to one of the first bit lines in response to the control signal, two of the first selecting transistors being coupled to a same one of the first bit lines and located on opposite sides of the one of the first bit lines, and a plurality of second selecting transistors having their gates coupled to the second selecting line to receive the control signal, each of the second selecting transistors coupled to one of the second bit lines, each of the second selecting transistors for coupling one of the memory cells in the selected row to one of the second bit lines in response to the control signal.

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Hong Kong, China

Ka Wai Cheung