Realtek Semiconductor Inc.

Ka-Un Chan

Hsiao-Tsung Yen

Po-Chih Wang

Chia-Jun Chang

Kuan-Yu Shih

Yi-Shao Chang

Ting-Yao Huang

Chao-Huang Wu

Han-Chang Kang

Chih-Lung Chen

Ying-Hsi Lin

Yu-Che Yang

Ping-Yuan Deng

Jian-You Chen

Hsien-Ku Chen

Chia-Yi Lee

Chin-Lung Li

Yi-Chang Shih

Wei-Ming Chiu

Chih-Chan Tu

Gen-Sheng Ran

Kuan-Hao Tseng

Shen-Iuan Liu

Chih-Yu Tsai

Chien-I Chou

Chia-jun Chang

Hung-Han Chen

Yung-Ming Chiu

Yang Chang

Yi-Ching Wu

Hung-Yu Tsai

Yong-Ru Lu

Teng-Yuan Chang

Chia-Liang Lin

Jon-Jin Chen

Hsiang-Chung Hsu

Sung-Jiun Tsai

Ping-Hsuan Tsai

Yang-Tang Tsai

Han-Ting Tsai

Rong-Fu Yeh

An inductor device includes a first trace, a second trace, and a capacitor. The first trace includes at least two sub-traces. One terminal of each of the at least two sub-traces are coupled to each other at a first node. The second trace includes at least two sub-traces. One terminal of each of the at least two sub-traces are coupled to each other at a second node. The capacitor is coupled to the first node and the second node.

Inductor device

A power amplifying circuit includes a first input terminal applied with a first bias voltage, a first amplifying circuit generating a first output signal and a second output signal according to an input signal and a first matching circuit combining the first output signal and the second output signal to generate an output signal. The first amplifying circuit includes a first transistor having a first electrode coupled to the first input terminal and a second electrode applied with a second bias voltage and a second transistor having a first electrode s coupled to the first input terminal and a second electrode applied with a third bias voltage. The first transistor generates the first output signal according to the first bias voltage and the second bias voltage. The second transistor generates the second output signal according to the first bias voltage and the third bias voltage.

Power amplifying circuits

An inductor device includes a first trace, a second trace, a third trace, a fourth trace, and a double ring inductor. The first trace is disposed in a first area, and located on a first layer. The second trace is disposed in the first area, coupled to the first trace, and located on a second layer. The third trace is disposed in a second area, and located on the first layer. The fourth trace is disposed in the second area, coupled to the third trace, and located on the second layer. The double ring inductor is disposed on the first layer, located at outer side of the first trace and the third trace, and coupled to the first trace and the third trace.

An inductor device includes a first trace, a second trace, and at least one connection member. The first trace is disposed on a first area. The second trace is disposed on a second area. The first area and the second area are coupled to each other at a junction. The at least connection member is disposed at a block at which the first trace and the second trace are not disposed and which is adjacent to the junction, and the at least connection member is coupled to the first trace and the second trace.

An inductor device includes a first wire, a second wire, and a third wire. The first wire includes a plurality of first sub-wires. The second wire includes a plurality of second sub-wires. The sequence of the first sub-wires and the second sub-wires is that at least two first sub-wires of the first sub-wires and at least one second sub-wires of the second sub-wires are disposed to each other in an interlaced manner. The third wire is disposed adjacent to at least two first sub-wires of the first sub-wires.

An inductor device includes a first trace, a second trace, and a capacitor. The first trace includes a first and a second sub-trace. The first sub-trace includes first wires, and the second sub-trace includes second wires. The second sub-trace is coupled to the first sub-trace at a first node. The first and the second wires are disposed to each other in an interlaced manner, and located at an outer side of the inductor device. The second trace includes a third and a fourth sub-trace. The third sub-trace includes third wires, and the fourth sub-trace includes fourth wires. The fourth sub-trace is coupled to the third sub-trace at a second node. The third and the fourth wires are disposed to each other in an interlaced manner, and located at an outer side of the inductor device. The capacitor is coupled between the first and the second node.

An inductor structure includes a first connecting component, a second connecting component, and a center-tap terminal. In the inductor structure, a first port of the first connecting component is coupled to a first wire, and a second port of the first connecting component is coupled to a second wire. The second connecting component disposed above or beneath the first connecting component in an interlaced manner. The center-tap terminal is coupled to one of the first connecting component and the second connecting component. The center-tap terminal is disposed on a layer that is different from the layer where the first connecting component is disposed or the layer where the second connecting component is disposed.

Inductor structure

An inductor device includes a first wire, a second wire, a third wire, a fourth wire and an 8-shaped inductor structure. The first wire is disposed in a first area. The second wire is disposed in a second area. The third wire is disposed in the first area and at least partially overlapped with the first wire in a vertical direction. The third wire includes at least two third sub-wires, and the at least two third sub-wires are arranged with an interval between each other. The fourth wire is at least partially overlapped with the second wire in the vertical direction. The fourth wire includes at least two fourth sub-wires, and the at least two fourth sub-wires are arranged with an interval between each other. The eight-shaped inductor structure is disposed on an outer side of the third wire and the fourth wire.

Eight-shaped inductor for use in integrated circuit structure having plurality of wires and each wire has at least two sub-wires

A transformer device includes a first coil, a second coil, and a third coil. The first coil includes a first ring structure, a second ring structure, a first connecting portion, and a first terminal, in which the first terminal is arranged on the first connecting portion and is located at a central location between the first ring structure and the second ring structure, the first terminal is connected to the first ring structure through the first connecting portion in a first direction, and connected to the second ring structure through the first connecting portion in a second direction, and the first direction is the opposite of the second direction. The second coil is configured to couple the first ring structure. The third coil is configured to couple the second ring structure, in which the second coil and the third coil have the same structure.

Transformer device

An inductor device includes a first coil, a second coil and a toroidal coil. The first coil is partially overlapped with the second coil in a vertical direction. The toroidal coil is disposed outside the first coil and the second coil. The first coil is interlaced with the second coil at a first side and a second side of the inductor device.

An asymmetric spiral inductor is provided. The asymmetric spiral inductor includes a first winding, a second winding and a third winding. The first winding has a first end and a second end and is implemented in the ultra-thick metal (UTM) layer of a semiconductor structure. The second winding, which has a third end and a fourth end, is implemented in the re-distribution layer of the semiconductor structure and has a first maximum trace width. The third winding, which has a fifth end and a sixth end, is implemented in the UTM layer of the semiconductor structure and has a second maximum trace width smaller than the first maximum trace width. The second and third ends are connected through a first through structure, the fourth and fifth ends are connected through a second through structure, and the first and sixth ends are the two ends of the asymmetric spiral inductor.

Asymmetric spiral inductor

An integrated circuit includes a first coil and a second coil. The first coil is disposed on the first side of the integrated circuit. The second coil is disposed on the second side of the integrated circuit, and is partially overlapped with the first coil at a junction. The first coil is not interlaced with the second coil at the junction.

Integrated circuit

An inductor device includes a first inductor, a first connection member, a second inductor, and a second connection member. The first inductor includes a first and a second trace. The first trace is disposed in a first area, and the second trace is disposed in a second area. The first and the second area are connected at a junction. The first connection member is disposed at a block at which the first and the second trace are not disposed, and coupled to the first and the second trace. The second inductor includes a third and a fourth trace. The third trace is disposed in the first area, and the fourth trace is disposed in the second area. The second connection member is disposed at a block at which the third and the fourth trace are not disposed, and coupled to the third and the fourth trace.

An inductor device includes a first trace, a second trace, and a capacitor. The first trace includes at least two sub-traces. One terminal of each of the at least two sub-traces are coupled to each other at a first node. The second trace includes at least two sub-traces. One terminal of each of the at least two sub-traces are coupled to each other at a second node. The capacitor is coupled to the firs node and the second node.

A stacked inductor device including an 8-shaped inductor structure a stacked coil. The 8-shaped inductor structure includes a first coil and a second coil. The first coil is disposed in a first area. The first coil includes a first sub-coil and a second sub-coil, and the first sub-coil and the second sub-coil are disposed with an interval circularly with each other. The second coil is disposed in a second area, and the second coil is coupled with the first coil on a boundary between the first area and the second area. The second coil includes a third sub-coil and a fourth sub-coil, and the third sub-coil and the fourth sub-coil are disposed with an interval circularly with each other. The stacked coil is coupled to the first coil and the second coil and is stacked partially on or under the first coil and the second coil.

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Hsinchu County, Taiwan

Ka-Un Chan