Qualcomm Incorporated

Apple Inc.

Lsi Corporation

Ka-Shu Ko

Yiliang L Bao

Ho-Ming Leung

Shu Xiao

Nasima Parveen

Abheek Banerjee

To improve video parser performance and reduce bottleneck, a video parser may parse a video stream to decode multiple symbols per clock cycle. By decoding multiple symbols per clock cycle, the video parser may decode symbols more quickly and efficiently compared to decoding one symbol per clock cycle, and thus may be less likely to act as a bottleneck for remaining video decoding operations.

Systems and methods for decoding multiple symbols per clock cycle

Techniques for decoding the run_before fields in a CAVLC encoded bitstream for H.264 are disclosed. In one aspect, the codewords corresponding to a plurality of consecutive initial zero-value run_before codewords are stored in a look-up table, allowing the decoding of such a plurality of run_before codewords in a single computation cycle. In another aspect, the look-up table is additionally configured to decode the next non-zero run_before value after the initial zero-value run_before codewords in the same computation cycle.

CAVLC run-before decoding scheme

An apparatus comprising an oscillator circuit, a control circuit, a counter circuit and a detector circuit. The oscillator circuit may be configured to generate an output signal oscillating at a particular frequency in response to a control signal. The control circuit may be configured to generate the control signal in response to a first error signal and a second error signal. The counter circuit may be configured to generate the first error signal in response to the output signal and an input signal. The detector circuit may be configured to generate the second error signal in response to the output signal and the input signal.

Low jitter and/or fast lock-in clock recovery circuit

Growing community of inventors

San Ramon, CA, United States of America

Ka-Shu Ko