Agency for Science, Technology and Research

Ka Fai Chang

Yong Han

Surya Bhattacharya

Vempati Srinivasa Rao

Roshan Weerasekera

Masaya Kawano

David Soon Wee Ho

Ying Ying Lim

Various embodiments may provide a semiconductor package. The semiconductor package may include a semiconductor chip, a first mold compound layer at least partially covering the semiconductor chip, and a redistribution layer over the first mold compound layer, the redistribution layer including one or more electrically conductive lines in electrical connection with the semiconductor chip. The semiconductor package may additionally include a second mold compound layer over the redistribution layer, and an antenna array over the second mold compound layer, the antenna array configured to be coupled to the one or more electrically conductive lines.

Semiconductor package and method of forming the same

Various embodiments may provide a semiconductor package. The semiconductor package may include a routing layer including a plurality of first layer contact elements on a first side and a plurality of second layer contact elements on a second side opposite the first side, and a first semiconductor die including a plurality of first electrical die contact elements coupled to the plurality of first layer contact elements. The semiconductor package may further include a second semiconductor die including a plurality of second electrical die contact elements coupled to the plurality of second layer contact elements, and a mold structure covering the second semiconductor die. A first pitch between neighbouring first electrical die contact elements may be greater than a second pitch between neighbouring second electrical die contact elements.

A fan-out wafer-level packaging method and the package produced thereof are provided in the present application. The method comprises steps including: providing a silicon substrate layer having a first thickness; forming one or more active/passive devices comprising at least sources and drains and one or more diffusion layers adjoining the sources and drains, wherein forming the one or more active/passive devices comprises forming the sources and the drains in a front-end-of-line (FEOL) layer on a first side of the silicon substrate layer while forming the one or more diffusion layers at locations in the silicon substrate layer adjoining the sources and the drains; forming a redistribution layer (RDL) over the FEOL layer by copper damascene formation of multiple metallization layers for connecting the one or more active/passive devices to the one or more IC dies when the one or more IC dies are mounted on a side of the RDL opposite the FEOL layer; thinning the silicon substrate layer to a second thickness to form a thinned silicon substrate, the thinned silicon substrate comprising at least the one or more diffusion layers; and patterning the thinned silicon substrate to form one or more silicon regions, each of the one or more silicon regions comprising the one or more diffusion layers.

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Singapore, Singapore

Ka Fai Chang