Texas Instruments Corporation

K R Udayakumar

Scott Robert Summerfelt

Theodore Sidney Moise

Sanjeev Aggarwal

Martin G Albrecht

Luigi Colombo

Howard R Beratan

Charles M Hanson

John Anthony Rodriguez

Francis Gabriel Celii

Kelly Jay Taylor

Lindsey H Hall

Sarah Hartwig

J Scott Martin

Jeff L Large

Sirisha Kuchimanchi

Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (C) from hydrogen diffusion in semiconductor devices (), wherein nitrided aluminum oxide (N&#x2014;AlOx) is formed over a ferroelectric capacitor (C), and one or more silicon nitride layers () are formed over the nitrided aluminum oxide (N&#x2014;AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N&#x2014;AlOx) is formed over the ferroelectric capacitors (C), with two or more silicon nitride layers () formed over the aluminum oxide (AlOx, N&#x2014;AlOx), wherein the second silicon nitride layer () comprises a low silicon-hydrogen SiN material.

Ferroelectric capacitor hydrogen barriers and methods for fabricating the same

Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.

Low silicon-hydrogen sin layer to inhibit hydrogen related degradation in semiconductor devices having ferroelectric components

Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.

Hydrogen barrier for protecting ferroelectric capacitors in a semiconductor device and methods for fabricating the same

Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (C) from hydrogen diffusion in semiconductor devices (), wherein nitrided aluminum oxide (N&#x2014;AlO) is formed over a ferroelectric capacitor (C), and one or more silicon nitride layers () are formed over the nitrided aluminum oxide (N&#x2014;AlO). Hydrogen barriers are also provided in which an aluminum oxide (AlO, N&#x2014;AlO) is formed over the ferroelectric capacitors (C), with two or more silicon nitride layers () formed over the aluminum oxide (AlO, N&#x2014;AlO), wherein the second silicon nitride layer () comprises a low silicon-hydrogen SiN material.

The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By so doing, the sidewall diffusion barrier layer(s) are substantially amorphous and provide superior protection against hydrogen diffusion than conventional and/or crystalline sidewall diffusion barrier layers.

Use of amorphous aluminum oxide on a capacitor sidewall for use as a hydrogen barrier

Apparatus and methods are described for a multi-level FeRAM memory device. Using write and read circuits associated with the memory device, multiple data states may be written to and read from the ferroelectric memory device which are associated with a single polarization direction, thereby allowing for a single cell to contain more than one bit of data.

Ferroelectric memory with wide operating voltage and multi-bit storage per cell

A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.

VIA0 etch process for FRAM integration

Ferroelectric materials useful in monolithic uncooled infrared imaging use Ca and Sn substitutions in PbTiO3 and also have alternatives with dopants such as Dy, Ho, Bi, Ce, and Fe. The ferroelectrics may also be used in non-volatile integrated circuit memories.

Growing community of inventors

Dallas, TX, United States of America

K R Udayakumar