International Business Machines Corporation

Siemens Aktiengesellschaft

Globalfoundries Inc.

Infineon Technologies North America Corp.

K Paul Muller

Edward J Nowak

William Vincent Huott

Kevin W Kark

William J Rooney

David S Wolpert

Ghavam G Shahidi

Andres Bryant

David Michael Fried

Reinhard Theodor Buendgen

James A O'Connor

Khary J Alexander

Craig Raymond Walters

Tiberiu (Jim) Suto

John Greg Massey

Luiz Carlos Alves

William J Clarke

David L Rude

Andrew H Vogel

Jed Hickory Rankin

Tze-Chiang Chen

Meikei Ieong

Fariborz Assaderaghi

Ethan Harrison Cannon

Daniel J Kearney

Emmanuel Yashchin

Rajeev Malik

Scott J Hadderman

Christopher Raymond Conklin

Sean M Swehla

Devendra K Sadana

Jack Allan Mandelman

Louis L Hsu

Tak H Ning

Dominic Joseph Schepis

Randy William Mann

Dieter F Wendel

Robert Brett Tremaine

James Douglas Warnock

Utz Bacher

Philip Joseph Oldiges

Werner A Rausch

John C Dayka

Paul David Agnello

Leon Jacob Sigal

Patrick Joseph Callaghan

Christopher D Sheraw

Thomas J Knips

Thomas B Mathias

Aj KleinOsowski

Kenneth C Arndt

Peter G Spera

Kurt Norman Schroeder

Katie L Pizzolato

Stefan Usenbinz

Bertrand Flietner

Timothy R Marchini

Alicia Wang

Rejean P Levesque

Alyssa C Bonnoit

Lars W Liebmann

Cyril Cabral, Jr

Brian Robert Prasky

Pradip Bose

Kenneth Parker Rodbell

Shreesh Narasimha

Malcolm Scott Ware

John C Forster

Marcel Mitran

Wei T Huang

Peter Bergersen Yocom

Hon-Sum Philip Wong

Natesan Venkateswaran

James A Culp

Scott David Halle

Guillermo Jesus Silva

Venkatachalam C Jaiprakash

Prabhakar Nandavar Kudva

Stefan Schmitz

Harbans S Sachdev

Scott Arthur MacDonald

Andrew A Turner

Michael J Lee

Kevin A Batson

Rajiv M Ranade

Stephen Larry Runyon

Eli Arbel

Eberhard Engler

Patrick M Williams

Joran S C Siu

Leo L Linehan

Uma Srinivasan

Walter E Mlynko

David F Heidel

Shiri Moran

Jayapreetha Natesan

Robert Van Den Berg

Klaus Dieter Penner

Andre I Nasr

Klaus Roithner

A method, system, and computer program product algorithmically analyzes scoring data from a competitive event where the scoring, determined by a plurality of evaluators, is based on subjective criteria. The method receives, and/or determines a scale factor associated with each evaluator. The method adjusts scores awarded by each evaluator, based on respectively corresponding scale factors, to arrive at normalized scores. The method, thereby minimizes influences of biases associated with the evaluators.

Detecting and removing bias in subjective judging

Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.

Tunable power save loop for processor chips

Pattern recognition is used to proactively treat defects of repeating circuit topologies. A component of a computing environment is monitored for failures. The component includes one or more repeating circuit topologies. A determination is made as to whether a new failure within a repeating circuit topology of the one or more repeating circuit topologies has occurred within a predefined amount of time from a previous failure matching a selected pattern, in which the selected pattern indicates a non-contiguous growing defect. Based on determining the new failure has occurred within the predefined amount of time from the previous failure matching the selected pattern, corrective action for the component is proactively taken.

Pattern recognition for proactive treatment of non-contiguous growing defects

An instruction control interface is provided for automatically controlling assigning of one or more instructions for processing by one or more processor cores of a computing device. The control interface separately monitors temperatures of multiple logic units within each processor core of the processor core(s) of the computing device, and controls assigning of one or more instructions for processing by a particular processor core(s) based, at least in part, on the separately monitored temperatures of the multiple logic units within the processor core(s). By separately monitoring temperature of logic units within a processor core, the interface automatically determines whether to assign the current instruction for execution without temperature-induced change, whether to reassign the instruction(s) to another processor core, whether to convert the current instruction to execute on different logic units of a particular processor core than the current instruction(s), or to reorder a sequence of execution of the instruction(s).

Thermal availability based instruction assignment for execution

Technical solutions are described for authenticating a hosting system prior to securely deploying a shrouded virtual server. An example method includes receiving, by a hypervisor, a request for a public certificate, from a client device that requested the virtual server, and sending the public certificate of the hosting system that executes the hypervisor. The method also includes receiving, in response to the public certificate being successfully authenticated by the client device using a third-party verification system, a session key based on a public key included in the public certificate. The method also includes decrypting the session key using a private key, where the private key is pre-installed in the hosting system by a manufacturer of the hosting system, and sending an acknowledgement message encrypted using the session key. The method also includes establishing a secure communication between the client device and the hypervisor using the session key.

Authenticating features of virtual server system

Technical solutions are described for securely deploying a shrouded virtual server. An example method includes sending, by a host manager, authentication information of a hosting system to a client device in response to a request from the client device. The \method also includes receiving a request to deploy a virtual server using a shrouded mode. The method also includes deploying a preconfigured hypervisor on the hosting system, where the preconfigured hypervisor is deployed in an immutable mode that disables changes to security settings of the preconfigured hypervisor. The method also includes deploying, by the preconfigured hypervisor, a preconfigured boot image as an instance of the virtual server on the preconfigured hypervisor. The method also includes sending, by the host manager, an identifier of the virtual server for receipt by the client device.

End-to end protection for shrouded virtual servers

End-to-end protection for shrouded virtual servers

A multiple processor core computer system interface assigns instructions to partially functional processor cores based on processing resources available in each partially functional core. Each processor core is labeled as fully functional, partially functional, or non-functional, and an indicator is provided for each partially functional processor core that shows what processing resources are available for a respective core. The indicators can be stored in memory after final test. The interface can monitor cores for changes in available resources and update respective indicators, such as by superseding an existing indicator with or creating a new indicator in read-write memory.

Computer system using partially functional processor core

A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.

Template matching for resilience and security characteristics of sub-component chip designs

Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.

Built-in testing of unused element on chip

A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.

Error protection for a data bus

Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of 'in-line' connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art 'side-by-side' transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in &#x201c;hardening&#x201d; of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.

In-line stacking of transistors for soft error rate hardening

A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.

Soft error resilient FPGA

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Wappingers Falls, NY, United States of America

K Paul Muller