Broadcom Corporation

K Naresh Chandra Srinivas

Ramanujan K Valmiki

Anand Pande

Presented herein is a scheme for reducing the likelihood of erroneous DQS signals. Logic is incorporated proximate to a memory controller and receives a signal indicating a read request and a DQS signal from a memory module. The logic transmits a signal indicating the presence of data, based on the timing relationship between the DQS signals and signal indicating read requests.

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Bengaluru, India

K Naresh Chandra Srinivas