Taiwan Semiconductor Manufacturing Comp. Ltd.

Jyy Anne Lee

Shyh-An Chi

Yun-Han Lee

Shiue Tsong Shen

A circuit includes a central processing unit (CPU), which includes a first memory block having a first power domain; and a core block signally connected to the first memory block and having a second power domain disconnected from the first power domain.

Separating power domains of central processing units

An integrated circuit includes a process voltage temperature (PVT) effect transducer responsive to a PVT effect, a PVT effect quantifier coupled to the PVT effect transducer and configured to quantify the PVT effect to provide an output, and a bias controller configured to receive the output of the PVT effect quantifier and provide a bias voltage for a substrate of an NMOS or a PMOS transistor. The bias controller is configured to compare the output received from the PVT effect quantifier to a threshold value, and decrease or increase the bias voltage depending on whether the output is higher or lower than the threshold value.

Substrate bias control circuit

A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator.

Substrate bias control circuit for system on chip

A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.

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Taipei, Taiwan

Jyy Anne Lee