Panasonic Corporation

Jyunichi Suenaga

Seiichi Moriyama

Mamoru Seike

Hiroyuki Kageyama

Kenji Yamashita

A display driving apparatus includes: n level shift units shifting a voltage level of n pixel data; a step potential providing unit providing a step potential; a change judgment unit judging whether or not each of the n pixel data has changed from pixel data of an immediately previous cycle; a delay unit generating n timing signals changing with different timings; and a control unit performing control such that the display output terminal corresponding to the pixel data judged to have changed by the change judgment unit is provided with: the step potential provided by the step potential providing unit during a first time period included in each of the cycle; and a potential shifted by the corresponding level shift unit during a second time period that is different from each other and is based on a timing of change of the corresponding timing signal.

Display driving apparatus, display module package, display panel module, and television set

A first latch circuit temporarily memorizes a display pixel data by one line. A second latch circuit temporarily memorizes the display pixel data as a preceding display pixel data that precedes the display pixel data by one line. The load judging circuit judges a transition state of the display pixel data based on the display pixel data and the preceding display pixel data and predicts a drive load capacity CL based on a result of the judgment. A drivability adjusting circuit adjusts a signal level of the display pixel data based on a result of the prediction of the drive load capacity CL and adjusts drivability of an output.

Display panel drive-control device and display panel drive-control method

A display driver includes: a first memory circuit for storing a line of pixels constituting an image; a second memory circuit for storing pixels of the immediately previous line; an output terminal pair switch circuit which outputs voltages each corresponding to a value of a pixel stored in the first memory circuit to a plurality of output terminals respectively corresponding to the pixels; and an inter-terminal load determination circuit for determining, for every pair of selected columns of pixels constituting the image, whether or not a short circuit is to be established between two of the plurality of output terminals which respectively correspond to the two selected columns based on values of at least three out of four pixels belonging to the two selected columns which are stored in the first and second memory circuits. If the inter-terminal load determination circuit determines that a short circuit is to be established, the output terminal pair switch circuit temporarily establishes a short circuit between the two output terminals before the voltages corresponding to the values of the pixels are output to the two output terminals.

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Osaka, Japan

Jyunichi Suenaga