Taiwan Semiconductor Manufacturing Comp. Ltd.

Jyuh-Fuh Lin

Shy-Jay Lin

Wen-Chuan Wang

Cheng-Hung Chen

Pei-Yi Liu

Burn Jeng Lin

Chih-Ming Ke

Te-Chih Huang

Guo-Tsai Huang

Cheng-Chi Wu

Jia-Rui Hu

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio rto optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

Method of fabricating an integrated circuit with non-printable dummy features

The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity

A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.

System and technique for rasterizing circuit layout data

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio rto optimize an uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for non-printable dummy features and adding the non-printable dummy features in the IC design layout.

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a plurality of main features; choosing isolation distances to the IC design layout; oversizing the main features according to each of the isolation distances; generating a space block layer for the each of the isolation distances by a Boolean operation according to oversized main features; choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout according to pattern density variation; generating dummy features in the optimized space block layer according to the optimized block dummy density ratio; and forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication.

Method of fabricating an integrated circuit with block dummy for optimized pattern density uniformity

The present disclosure provides a method that includes receiving an IC design layout having main features and generating a plurality of space block layers to the IC design layout. The method also includes calculating main pattern density PDand dummy pattern density PDof the IC design layout and calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space block layers according to the main pattern density and the dummy pattern density. The method further includes choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR and generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio. Additionally, the method includes forming a tape-out data of the modified IC design layout for IC fabrication.

Method of fabricating an integrated circuit with optimized pattern density uniformity

In one embodiment, a method for detecting design defects is provided. The method includes receiving design data of an integrated circuit (IC) on a wafer, measuring wafer topography across the wafer to obtain topography data, calculating a scanner moving average from the topography data and the design data to provide a scanner defocus map across the wafer, and determining a hotspot design defect from the scanner defocus map. A computer readable storage medium, and a system for detecting design defects are also provided.

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Miaoli County, Taiwan

Jyuh-Fuh Lin