Samsung Electronics Co., Ltd.

Freescale Semiconductor,inc.

Jyotsna Kartha

Vikas Sinha

Eric C Quinnell

Brian C Grayson

Kathryn C Stacer

A method and apparatus are provided. The apparatus includes a plurality of central processing units, a plurality of core input/output units, a plurality of last level cache memory banks, an interconnect network comprising multiple instantiations of dedicated data channels, wherein each dedicated data channel is dedicated to a memory transaction type, each instantiation of dedicated data channels includes arbitration multiplexors, and each dedicated data channel operates independently of other data channels.

Non-uniform bus (NUB) interconnect protocol for tiled last level caches

A cache management system employs a replacement policy in a manner that manages concurrent accesses to cache. The cache management system comprises a cache, a replacement policy storage for storing replacement statuses of cache lines of the cache, and an update module. The update module, comprising access filtering and a concurrent update handling, determines how updates to the replacement policy storage are handled. In a multi-threaded compute environment, a concurrent access to shared cache causes a selective update to the replacement policy storage.

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Austin, TX, United States of America

Jyotsna Kartha