Nvidia Corporation

Jyotirmaya Swain

Edward L Riegelsberger

Utpal Barman

Anirban Ghosh

Hari Unni Krishnan

Padam Patt Krishnani

Avinash J V

Michael Alan Ditty

Shraddha Manohar Gondkar

Phanikumar Parvatham

Adarsh Kalliat

Raji Cherian

Harshil Jain

Swapnil Tapadia

Various embodiments include techniques for processing transactions via a computer system interconnect with a distributed firewall. The distributed firewall includes separate firewalls for various initiators of transactions and separate firewalls for various targets of those transactions. As a result, transactions proceed, for example, along the shortest path from the initiator to the target, rather than being routed through a centralized firewall. In addition, firewall transactions, for example, may be remapped such that initiators address the initiator firewalls and target firewalls via a unified address space, without having to maintain separate base addresses for each initiator firewall and target firewall. As a result, application programs, for example, can execute transactions with increased performance on a computer system as compared to prior approaches.

Physically distributed control plane firewalls with unified software view

In various examples, a system includes a memory operating within a first risk level and circuitry operating within a second risk level that indicates more risk than the first risk level. The circuitry reads and/or writes data to a first memory address within the memory, and reads and/or writes an error detection code to a second memory address within the memory.

Transmitting data between regions of varying safety integrity levels in a system on a chip

According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge ('first edge') of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.

Programmable delay circuit providing for a wide span of delays

Read leveling of memory units designed to receive access requests in a sequential chained topology writing a data pattern to the memory array. In an embodiment, a memory controller first writes a desired pattern into the memory array of a memory unit and then iteratively determines the accurate calibrated delay by setting a compensation delay to a test value, reading a data portion from the memory array based on the test value for the compensation delay, comparing the data portion with an expected data, determining that the test value is a calibrated compensation delay for the memory unit if the data portion equals the expected value.

Read leveling of memory units designed to receive access requests in a sequential chained topology

A memory controller provided according to an aspect of the present invention uses a slower clock signal during write leveling compared to when performing write operations thereafter. Due to such use of a slower clock signal, the various desired delays can be determined accurately and/or easily. In an embodiment, the frequency of the slower clock signal is determined based on the maximum fly-by delay (generally the delay between sending of a signal on the shared sequential path and the receipt at the memory unit in the sequence) that may be present in the memory system. For example, if the fly by delay can be M (an integer) times the time period of the clock signal during normal write operations, the slower clock signal may have a time period of M times that of the clock signal during write operation.

Write leveling of memory units designed to receive access requests in a sequential chained topology

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Bengaluru, India

Jyotirmaya Swain