Gsi Technology, Inc.

Intelleflex Corporation

Sierra Semiconductor

Neoaxiom Corporation

Acard Technology Corporation

Xaqti, Corporation

Jyn-Bang Shyu

Lee-Lean Shu

Jae Hyeong Kim

David Y Wang

Robert Olah

Yoshinori Sato

Roubik Gregorian

Ta-wei Yang

Roger Green Stewart

Rohit Mittal

Yu-Chi Cheng

Lance K Lee

Jin Zhao

Larry Farnsley

Thomas Ching

Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.

Systems and methods involving phase detection with adaptive locking/detection features

The present disclosure relates to systems and methods of noise reduction and/or power saving. According to one or more illustrative implementations, for example, innovations consistent with delay lines in clock/timing circuits such as Delay-Lock-Loop (DLL) and/or Duty Cycle Correction (DCC) circuits are disclosed.

Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines

A circuit for recovering data from an incoming data stream according to one embodiment includes a capacitor and a substantially constant current source for charging the capacitor. A subcircuit generates a signal causing the capacitor to discharge upon detecting a first type of transition in the incoming data stream, the capacitor re-charging upon being at least partially discharged. A comparator compares a voltage on a node coupled to the capacitor to a reference voltage, the comparator outputting a first signal if the voltage on the node is higher than the reference voltage and outputting a second signal if the voltage on the node is lower than the reference voltage, the first signal being associated with a first logic value, the second signal being associated with a second logic value.

Clock-free activation circuit

A radio frequency circuit for summing signals from multiple lobes of an antenna includes circuitry for converting RF signals from lobes of an antenna to baseband signals, and circuitry for summing the baseband signals from the lobes of an antenna.

Compact omni-directional RF system

Fully differential amplifier circuits are described herein that set the common mode voltage as well as reduce the output offset voltage (offset cancellation). A circuit according to one embodiment includes a first section for generating first and second output signals on first and second outputs from first and second input signals, a first negative feedback loop coupled to the first section, and a second negative feedback loop coupled to the first section. A second section controls the first negative feedback loop for adjusting the first output signal towards a common mode voltage level, and for reducing an offset voltage of the first output signal in different loop bandwidths. A third section controls the second negative feedback loop for adjusting the second output signal towards the common mode voltage level, and for reducing an offset voltage of the second output signal in different loop bandwidths.

Fully differential amplifier with continuous-time offset reduction

Systems with semiconductor devices that are DC-biased at either their weak inversion (i.e., sub-threshold) region or their strong inversion region. In a preferred embodiment using semiconductor devices (e.g., NMOS, PMOS, etc.), a gate to source voltage (Vgs) is slightly below the threshold voltage (Vtn) of the device. These weakly turned-on semiconductor devices increase the receiving AC sensitivity of an AM-Detector compared to that of a conventional AM-Detector without any DC-biasing. Further, the compensating bias voltage (Vbias) compensates for one or both of the ambient temperature change and the foundry's process variation of the various semiconductor devices.

Differential input circuit with process variation and temperature compensation

a circuit for an RFID device in one embodiment includes an operational amplifier having a first input, a second input, and an output where the first input receives an incoming signal, arid the second input is coupled to the output via a feedback loop. An operational amplifier for an RFID device according to another embodiment compares an output of the operational amplifier to an incoming baseband signal, A circuit according to another embodiment includes an operational amplifier having a first input, a second input, and an output, wherein the first input receives an incoming signal, and wherein the second input is coupled to the output via a feedback loop. A comparator having one input is coupled to the output of the operational amplifier, another input receiving the incoming signal, and an output for outputting an outgoing signal. Methods for adjusting a filtering characteristic of an operational amplifier are also disclosed.

Circuitry for adaptively generating and using a reference voltage

A clock data recovery (CDR) circuit that can be used for recovering data from a high-speed serial transmission using components that operate at a fraction of the data speed. The CDR consists of a phase detector, an averaging circuit and a phase interpolator. The phase detector samples each data bit at its midpoint and at its transitional region and then compares the two samples to determine whether the sampling clock, which is generated by a phase interpolator, is leading or lagging the data stream. The averaging circuit filters out the high frequency jitters in the phase detector output and then passes the filtered signals on to the phase interpolator for phase selection. The phase interpolator uses the filtered signals from the averaging circuit as a guide in the selection of an output clock phase that minimizes the phase difference between the output clock and the incoming data.

Method and apparatus for high-speed clock data recovery using low-speed circuits

A method and a lock detector circuit for phase-locked loop for detecting lock between reference signal and a feedback signal in two phases: lock detection phase and lock assertion phase. The detector circuit comprises delay circuits coupled to a first, a second D flip flops, an OR logic gate, and an AND gate. In the lock detection, the lock detector circuit compares the phases of the reference input clock with the feedback clock. If the phases of these clocks are different or not within a window of tolerance, the sample clock outputs of the first and second D flip flops are different. This condition causes the logic gate to issue a reset signal to the divide-by-64 counters. As such, the lock detection signal is low, indicating the PLL is not in lock condition. In the lock assertion phase, if the two phases are the same or within the window of tolerance, the sample clock outputs of the first and second D flip flops are the same or both low at the same time. This condition causes the logic gate to issue an enabling signal to the divide-by-64 counters. The divide-by-64 counter starts to count to full cycle and then the lock detect signal is high, indicating the PLL is in locked condition.

Cross clocked lock detector circuit for phase locked loop

A loop filter circuit in a phase lock loop, which also includes a phase detector, a charge pump, and a voltage controlled oscillator (VCO). The loop filter circuit is comprised of two active filters and a common mode feedback control differential comparator (CMFCDC). The active filters process differential signals from the charge pump and output a pair of differential signals to the VCO. The CMFCDC provides a common mode feedback path to both active filters. The loop filter circuit eliminates common mode noise introduced by power supply and ground, and reduces phase jitter in the overall PLL circuits. Each of the active filters is comprised of two independent sets of passive elements that dictate the values of natural modes (poles) and transmission zeros (zeros) of the filtering modules. This allows PLL designers wider latitude in adjusting the unity gain bandwidth of the active loop filter, which contributes to a more stable and better performing PLL circuit.

Differential active loop filter for phase locked loop circuits

Disclosed is a data/clock recovery system for use in a high speed networking transceiver units. The data/clock recovery system includes a four phase sampler circuit that is configured to receive a data input waveform and produce output data. A transition detect circuit that is arranged to receive the output data produced by the four phase sampler circuit. The transition detect circuit is configured to determine whether a clock is leading or lagging the data input waveform. A counter for shifting the clock if the clock is determined by the transition detect circuit to either be leading or lagging the data input waveform, such that the shifting is configured to synchronize the clock and the data input waveform. A decoder that receives control signals from the counter, such that the decoder generates a selection signal. The data/clock recovery system further including a multiplexer for selecting four predetermined clock phases in response to the selection signal generated by the decoder. Preferably, the four predetermined clock phases are continually shifted by the counter if the clock and the data input waveform are not synchronized.

Multi-phase data/clock recovery circuitry and methods for implementing same

A single pin integrated oscillator circuit includes an amplifier having a first input terminal to which an external crystal may be connected, and a second input terminal which receives a feedback path from an output terminal of the amplifier. An oscillator output signal having a relatively large voltage swing is provided from the first input terminal through a buffer. The oscillator operates over a wide range of voltages and process variations, and it can accept an input signal from an external crystal or can accept any clock signal having a swing of approximately 1 V.

Growing community of inventors

Cupertino, CA, United States of America

Jyn-Bang Shyu