Cirrus Logic Inc.

Other

Jyhfong Lin

Bruce A Doyle

Zhong-Xuan Zhang

Yun-Ti Wang

A sense amplifier circuit is incorporated within a computer system and utilizes a latch coupled to an equalizing transistor that operates in the triode region and initially equalizes the sense amplifier circuit data outputs, the latch subsequently develops a voltage difference in response to a control signal, deactivation of the control signal then turns off the equalizing transistor thereby allowing the latch circuit to lock the developed voltage differential to full-swing across the sense amplifier data outputs.

Low power, single-phase latch-type current sense amplifier

A latch-type current sense amplifier circuit generates complementary latched data outputs indicative of a difference between first and second input currents provided to the sense amplifier circuit respectively via first and second input data lines. Included in the sense amplifier circuit are a latch circuit formed from cross-coupled inverters, a transmission gate responsive to a first control signal for equalizing the outputs of the sense amplifier circuit, and three transistors. The first transistor is responsive to a second control signal, activated after a delay after deactivation of the first control signal, for connecting a reference voltage to the latch circuit. The second transistor has a source connected to the first input data line, a drain connected to a first input of the latch circuit, and a gate connected to a second output of the latch circuit such that the second transistor is initially in a saturated conducting state immediately after deactivation of the first control signal and consequently, serves to reduce the effect of the high input impedance of the latch circuit. The third transistor has a source connected to the second input data line, a drain connected to a second input of the latch circuit, and a gate connected to a first output of the latch circuit such that the third transistor is also initially in a saturated conducting state immediately after deactivation of the first control signal and consequently, also serves to reduce the effect of the high input impedance of the latch circuit.

Latch-type current sense amplifier with self-regulating inputs

A high speed CMOS current switching circuit suitable for use in digital to analog converters for graphic interfaces having high pixel clock rates, and such interfaces as may be used in portable and other battery operated or low power consumption applications. In operation, the current switching circuit normally steers an idle current to ground. If the bit of the digital to analog converter input digital signal represented by the respective source is a 1, the input signal representing the bit is delayed slightly while the current steered to ground is increased from the idle value to the full desired output current, whereupon at the end of the delay, the device coupling the output current to ground is turned off, thereby forcing the output current through an output device. A low power current steering circuit which can perform dynamic current steering without affecting switching speed performance is also disclosed. During the mode `off,` the path from current source to ground is completely cut off, so that at this mode there is no power consumption. Prior to turning to the `on` mode, the current source I.sub.B is first turned on to establish a stable current and to bias all the related nodes. The current steering circuitry is then turned to mode `on` to achieve a smooth transition. Similarly, the transition from mode `on` to `off` is achieved by steering the current to ground first and then cutting off the current source. Various embodiments are disclosed.

Low power high speed CMOS current switching circuit

A sense amplifier circuit includes a voltage developing stage which receives first and second data inputs, din1 and din2, and generates a differential voltage, in response to feedback signals received from a first and second data outputs, dout1 and dour2, of the sense amplifier circuit, which is indicative of a voltage difference between the first and second data inputs, din1 and din2; a full-swing locking stage which generates and latches, in response to a control signal .PHI..sub.2 ', complementary latched data outputs from the first and second data outputs, dout1 and dout2, generated by the voltage developing stage; and a voltage equalization stage which equalizes, in response to a control signal .PHI..sub.0 ', voltages on data lines respectively connected to the first and second data outputs, dout1 and dout2. In addition, the voltage equalization stage is used to initiate the voltage developing stage. Timing of the control signals, .PHI..sub.0 ' and .PHI..sub.2 ', is such that the control signal .PHI..sub.2 ' is activated after a finite period following the deactivation of the second control signal .PHI..sub.0 '. To minimize power consumption of the sense amplifier circuit, the control signal .PHI..sub.0 ' is deactivated when either the voltage developing or full-swing locking stage is in operation and the voltage equalization stage is not needed.

Low-voltage high-performance dual-feedback dynamic sense amplifier

A sense amplifier circuit includes a voltage developing stage which receives first and second data inputs, din1 and din2, and generates, in response to a first control signal .PHI..sub.1, a differential voltage indicative of a voltage difference between the first and second data inputs, din1 and din2; a full-swing locking stage which generates and latches, in response to a second control signal .PHI..sub.2, first and second latched data outputs, dout1 and dout2, from the differential voltage generated by the voltage developing stage; and a voltage equalization stage which equalizes, in response to a third control signal .PHI..sub.0, voltages on data lines respectively connected to the first and second data outputs, dout1 and dout2. Timing of the first, second and third control signals, .PHI..sub.1, .PHI..sub.2 and .PHI..sub.0, is such that the first control signal is activated after a finite period following the initial activation of the third control signal .PHI..sub.0, and the second control signal .PHI..sub.2 is activated after a finite period following the initial activation of the first control signal .PHI..sub.1. To minimize power consumption of the sense amplifier circuit, the first control signal .PHI..sub.1 is deactivated when the full-swing locking stage is in operation and the voltage developing stage is not needed, and the third control signal .PHI..sub.0 is deactivated when either the voltage developing or full-swing locking stage is in operation and the voltage equalization stage is not needed.

Growing community of inventors

Fremont, CA, United States of America

Jyhfong Lin