Via Technologies, Inc.

Jyhfong Lin

Hsin-Chieh Lin

Jiin Lai

Shan-Shan Lee

You-Ming Chiu

Wei-Yu Wang

Cheng Kuo Yang

Chin-Chang Chien

Yibin Hsieh

Chan-Hsiang Hsu

Yuwen Swei

A switch control circuit of an auto laser power control circuit is disclosed. The auto laser power control circuit has a feedback circuit and a switch control circuit. The switch control circuit has a first electronic switch, a second electronic switch, a third electronic switch, a fourth electronic switch, and a resistor. When a first control signal is enabled, the first electronic switch and the third electronic switch conduct and the second electronic switch and the fourth electronic switch are turned off. The signal of the feedback amplifying circuit is received by the driving circuit for driving a laser diode. When the first control signal is disabled, the second electronic switch and the fourth electronic switch conduct while the first and the third electronic switches are turned off. Via the voltage formed across the resistor in the driving circuit, the driving circuit is disabled, and the laser diode is completely turned off.

Switch control circuit of auto laser power control circuit

A phase lock loop (PLL) clock generator with programmable frequency and skew is provided in the present invention, in which frequency of clock signals generated can be dynamically changed and skew of the clock signals generated can be dynamically adjusted by a computer program. Also, the signal skew due to the change of loading can be compensated. Therefore, the PLL clock generator based on a closed-loop configuration can better control the skew of clock signals to provide higher stability and durability to the system.

Phase lock loop (PLL) clock generator with programmable skew and frequency

An automatic gain control circuit and control method. A variable gain amplifier amplifies a differential input signal. The amplified signal is passed to a filtering circuit for filtering. The amplitude of the filtered output signal is checked using a peak value inspection circuit. The result of inspection is used to set the gain of the variable gain amplifier and further adjust the amplitude of the output signal. The peak value inspection circuit comprises a non-inverted phase differential comparator, an inverted phase differential comparator, an OR gate and a charge/discharge circuit. The output signal is compared with a reference signal through two differential comparators. The result of comparison controls the charge/discharge circuit so that the gain of the variable gain amplifier is varied and the amplitude of the output signal is controlled.

Automatic gain control circuit and control method

A non-integer frequency divider that is capable of dividing an original clock frequency by a non-integer number into a desired target clock frequency. By this non-integer frequency divider, a phase-shifting circuit is first used to convert the original clock frequency into a predetermined number of phase-shifted versions of the original clock frequency with a predetermined phase difference. Then, a plurality of edge-triggered clock signal generators are used to generate a plurality of edge-triggered signals whose rising and falling edges are synchronized with the original clock frequency and its phase-shifted versions. Finally, a synthesis circuit is used to synthesize the edge-triggered signals into an output signal serving as the intended target clock frequency.

Non-integer frequency divider

A low clock feed through charge pump circuit applied in a phase includes a first pump transistor, a second pump transistor, a first switch device, a second switch device, a third switch device, a fourth switch device, a first wide-swing current mirror circuit and a second wide-swing current mirror circuit. Each of the first and second wide-swing current mirror circuits consists of four cascode transistor circuits and a bias circuit for providing a bias required by the low clock feed through charge pump circuit. The transistors forming the four switch devices and the four cascode transistor circuits operates in the saturation region. With the low clock through charge pump circuit, charge injection and jitter can be reduced.

Low frequency clock feed-through charge pump circuit

A signal-testing device used with a tester for testing a first signal and a second signal includes a selected signal generator receiving first signal and second signal for generating a selected signal the state of which is changed when first signal and second signal are in specific states, and a signal selector for selectively outputting one of first and second signals in response to the selected signal state. The present invention also provides a signal-testing method including steps of a) generating a selected signal having a plurality of pulses in response to a first signal and a second signal, b) obtaining a plurality of time differences between times when two inter-adjacent respective pulses respectively reach a specific voltage, c) obtaining a plurality of absolute values between two inter-adjacent respective time differences, and d) obtaining a phase difference by dividing by 2 an average value of the absolute values.

Method and device for signal testing

A low-voltage, low-jitter voltage controlled oscillator according to the invention includes a plurality of delay units electrically connected in series to form a closed loop circuit. Each delay unit has a symmetric differential structure constituted by a plurality of MOS FETs. Furthermore, only two transistors are stacked between the power source and ground. Thus, the low-voltage, low-jitter voltage controlled oscillator can operate at low voltage, and can not be affected by the variation of the power source voltage.

Low-voltage, low-jitter voltage controlled oscillator

A low-jitter delay locked loop having an expanded phase locking range without the necessity of setting the initial delay is provided. The loop is to be supplied by a system clock and includes a pulse generator receiving the system clock for generating a first pulse signal and a second pulse signal in response to a triggering signal, a delay device receiving the system clock for providing a delayed clock in response to a control signal, a frequency-reducing device for frequency-reducing the system clock into a first clock in response to the first pulse signal and frequency-reducing the delayed clock into a second clock in response to the second pulse signal, and a comparator for comparing the first and second clocks to generate the control signal.

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Taipei, Taiwan

Jyhfong Lin