Sun Microsystems, Inc.

Jyh-Ming Jong

Leo Yuan

Brian L Smith

Prabhansu Chakrabarti

Chung-Hsiao Wu

Wai Fong

Drew George Doblar

Jurgen M Schulz

Jue Wu

Daniel R Cassiday

Lee A Warner

Derek Tsai

Cecilia T Chen

A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

Automated calibration of I/O over a multi-variable eye window

A device configured to recover and repeat source synchronous data. The device is configured to receive source synchronous data via a first interface and recover the received data utilizing a first clock signal which is generated to be approximately ninety degrees out of phase with the received clock signal. A second clock signal is generated to be in phase with the received source synchronous clock signal. The second clock signal is the utilized to select a newly generated clock signal and latched data for transmission in a source synchronous manner. The device is further configured to shift the phase of the generated first clock signal to be approximately ninety degrees out of phase with the received data signal.

Source synchronous I/O bus retimer

A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data utilizing a corresponding received source synchronous clock signal, and transmit the recovered data and a corresponding clock signal in a source synchronous manner. In one embodiment, the device is configured to operate as a repeater without benefit of an internal clock signal. In addition, the device may be configured to remove data jitter and renew or restore amplitude to attenuated signals prior to retransmission.

Source synchronous bus repeater

A noise margin self-diagnostic receiver circuit has been developed. The self-diagnostic circuit includes one comparator for comparing the signal voltage to a high reference voltage, a second comparator for comparing the signal voltage to a low reference voltage, and a logic circuit that activates an alarm if a noise error is detected. The circuit analyzes the data from the comparators and determines if a noise error has occurred dependent on being clocked by one or both of an output from the comparator comparing the signal voltage to the high reference voltage and an output from the comparator comparing the signal voltage to the low reference voltage.

Noise margin self-diagnostic receiver logic

An optical transmitter for transmitting a first output data signal and a second output data signal, the optical transmitter comprising: a phase-locked-loop, the phase-locked-loop operable to receive a reference clock signal; a clock-recovery circuit, the clock-recovery circuit coupled to the phase-locked-loop, the clock-recovery circuit operable to receive a first input data signal; a latch-decision circuit, the latch-decision circuit coupled to the clock-recovery circuit; a latch, the latch coupled to the latch-decision circuit, the latch operable to receive the first input data signal and the second input data signal; a first electro-optical converter, the first electro-optical converter coupled to the latch, the first electro-optical converter operable to transmit the first output data signal; and a second electro-optical converter, the second electro-optical converter coupled to the latch, the second electro-optical converter operable to transmit the second output data signal.

Optical transmitter for transmitting a plurality of output signals

A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal. The resetting of the source synchronous receiver may be performed locally, and does not reset the core logic of the device in which it is implemented, nor any other source synchronous port on the device. Thus, other source synchronous ports on the device, as well as the core logic, may be able to continue operations as normal. The method and apparatus may include a source synchronous receiver that is hot-swappable.

Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection

A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a device under test (DUT) and may be mounted to a load board for testing. The load board may be electrically coupled to a test system. The test system may shift first test data into a first IC on the load board. The first chip may then transmit the first test data through a source synchronous line, or a source synchronous link having a plurality of lines, to a second IC. Second test data produced responsive to the source synchronous transmission is then shifted from the second IC to the tester. The second test data is then analyzed. The analysis may comprise comparing the second data to expected data, and/or may also comprise analyzing the second data with respect to an eye window.

System and method for testing operational transmissions of an integrated circuit

A data strobe receiver that includes a first comparator. The first comparator has a first input that is coupled to a first reference voltage. The first comparator has a second input that is coupled to a data strobe. The first comparator also has an output. The data strobe receiver also includes a delay element. The delay element has an input that is coupled to the output of the first comparator. The delay element also has an enable input and an output. The data strobe receiver also includes a second comparator. The second comparator has a first input that is coupled to a second voltage reference. The second comparator has a second input that is coupled to the data strobe. The second comparator also has an output. The data strobe receiver also includes a divide-by-X-counter, where X is an integer greater than 1 and less than 129. The divide-by-X-counter has an input that is coupled to the output of the second comparator.

Double data rate (DDR) data strobe receiver

One embodiment of the present invention provides a system for detecting a valid clock signal at a clock receiver. The system operates by receiving a clock signal at the clock receiver, and directing the clock signal into a control input of a voltage-controlled variable resistor. Next, the system uses the voltage-controlled variable resistor to control a first current. A current mirror is then employed to create a second current from the first current. This second current passes through a resistor to produce a control voltage, which is amplified to produce a validity signal indicating whether or not the clock signal is valid. In one embodiment of the present invention, the system additionally uses at least one capacitor to filter out periodic fluctuations in the validity signal.

Method and apparatus for detecting valid clock signals at a clock receiver circuit

A bi-directional output buffer includes active termination and separate driving and receiving impedances. The buffer has at least a driving mode and a receiving mode. In driving mode, the output impedance of the buffer is calibrated to a specified strength. In receiving mode, the buffer is calibrated to another specified impedance as an active termination. In addition, the buffer may be configured such that resistive components are shared in driving and receiving modes.

Bi-directional output buffer

An on-chip DC voltage generator providing a marginable reference voltage signal is described. The present invention is a CMOS-based integrated circuit that generates a marginable reference voltage level. The present invention provides a process insensitive reference voltage signal and may be configured so as to generate a ground-bounce-noise free signal.

Apparatus for on-chip reference voltage generator for receivers in high speed single-ended data link

A method and circuitry for pre-emphasizing transmitted logic signals. The method and circuitry may be applied to single-ended center-taped terminated I/O lines. In one embodiment, a driver circuit may be configured for monitoring the logic values (i.e. logic 0, logic 1, or logic low, logic high) of signals transmitted by the driver circuit. The driver circuit may compare the logic value of a next logic signal to be transmitted with a first previously transmitted signal and a second previously transmitted signal. Pre-emphasis of the next logic signal may occur based on the logic value of the next logic signal to be transmitted as well as the logic values of the first and second logic signals. If the first and second logic signals have the same logic value, and the next logic signal has a different value, the next logic value may be pre-emphasized. If the next logic signal has a logic value that is equivalent to either the first logic signal or the second logic signal, it may be transmitted without pre-emphasis.

Method and circuitry for a pre-emphasis scheme for single-ended center taped terminated high speed digital signaling

A data strobe receiver that includes a first comparator. The first comparator has a first input that is coupled to a first reference voltage. The first comparator has a second input that is coupled to a data strobe. The first comparator also has an output. The data strobe receiver also includes a delay element. The delay element has an input that is coupled to the output of the first comparator. The delay element also has an enable input and an output. The data strobe receiver also includes a second comparator. The second comparator has a first input that is coupled to a second voltage reference. The second comparator has a second input that is coupled to the data strobe. The second comparator also has an output. The data strobe receiver also includes a flip-flop. The flip-flop has a preset input that is coupled to the output of the second comparator. The flip-flop has a clock input that is coupled to the output of the delay element. The flip-flop also has an output that is coupled to the enable input of the delay element.

Data strobe receiver

A process tracking reference voltage generator has been developed for an input/output system. The voltage generator includes a driver component that transmits an output signal to a receiver component. The receiver component generates a reference voltage in relation to the output signal as it varies with changing system operating conditions.

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Saratoga, CA, United States of America

Jyh-Ming Jong