United Microelectronics Corp.

Jyh-Kuang Lin

Sheng-Hsing Yang

Joe Ko

Tz-Guei Jung

Chia-Hsin Hou

Ta-chi Kuo

Nai Jen Yeh

Ta-Chi Kuo

A method for fabricating a capacitor is applicable to a fabrication process for a mixed circuit. The method involves forming a first dielectric layer, a stop layer, and a second dielectric layer on a substrate having a conductive region. A first opening is then formed in the second dielectric layer, followed by forming a second opening in the stop layer and the first dielectric layer, so that the first opening and the second opening form a dual damascene opening for exposing the conductive region. The dual damascene opening is filled with a first conductive layer, so as to form a via plug and a lower electrode of the capacitor for connecting to the conductive region. A third dielectric layer, which is located between the lower electrode and a subsequent formed upper electrode, is then formed over the substrate, so that the lower electrode and a part of the second dielectric layer adjacent to the lower electrode are completely covered by the third dielectric layer. A patterned second conductive layer is formed on a part of the third dielectric layer, whereby an upper electrode for completely covering the lower electrode is formed.

Method of fabricating a mixed circuit capacitor

A new method of forming an integrated circuit MNOS/MONOS device with suppressed off-cell leakage current is described. A silicon oxide layer is formed on the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon oxide layer and patterned. A first ion implantation is performed at a tilt angle to form channel stop regions in the semiconductor substrate not covered by the patterned silicon nitride layer wherein the channel stop regions partially extend underneath the patterned silicon nitride layer. The silicon substrate not covered by the patterned silicon nitride layer is oxidized to form field oxide regions within the silicon substrate wherein the channel stop regions extend under the full length of the field oxide regions. The patterned silicon nitride layer is removed. An insulating layer of silicon nitride/silicon oxide (NO) or silicon oxide/silicon nitride/silicon oxide (ONO) is deposited over the surface of the semiconductor substrate. A layer of polysilicon is deposited overlying the insulating layer and patterned. Source and drain regions are formed within the semiconductor substrate to complete the MNOS/MONOS device with constant threshold voltage in the fabrication of an integrated circuit.

Method of forming an MNOS/MONOS by employing large tilt angle ion

A MOSFET semiconductor, erasable programmable ROM device on a lightly doped semiconductor substrate comprising field oxide regions in the semiconductor substrate. The field oxide regions extends down into sunken regions in the substrate through the openings. At least one of the field oxide regions is removed from the substrate to provide an opened one of the sunken regions in the substrate below the removed one of the field oxide regions. Ion implanted regions lie in the substrate below the openings. A gate oxide layer over the opened sunken region, and a floating gate over the gate oxide layer. Preferably, a tunnel oxide region is formed on the surface of the device with the floating gate overlying the tunnel oxide region to form an EEPROM device. The exposed sunken region has a V-shaped cross section sunken region extending deep into the substrate.

Method of manufacture of high coupling ratio single polysilicon floating

A process for fabricating semiconductor devices having lightly-doped regions in its drain and/or source. The semiconductor device has a gate structure formed on its substrate, and the sidewalls of the gate structure covered by sidewall spacers. The sidewall spacers having a selected thickness obstructs the impurity implantation and constitutes a lightly-doped region in addition to the relatively heavily-doped regions that are not obstructed during the implantation process. Both the lightly- and heavily-doped regions together constitute the drain and/or source of the semiconductor device.

Process of fabricating semiconductor devices having lightly-doped drain

An improved structure and process of fabricating a programmable and erasable read only memory device wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide region is removed forming a depression in the surface. Impurity ions are implanted into the depression forming a lightly doped source region. A tunnel oxide layer is formed on the substrate surface. Next, the floating gate layer is formed on the tunnel oxide layer which at least partially overlies the lightly doped source region. A gate insulation layer and control gate layer are formed over the floating gate layer. Subsequently, the source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact opening are formed. Electrical contacts and metallurgy lines with appropriate passivation are formed that connect the source, drain and control gate to form an electrical programmable memory device.

Method of making electrically programmable and erasable memory device

An improved structure and process of fabricating an electrically erasable programmable read only memory device (EEPROM's) wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide is removed forming a depression in the surface. Impurity ions are implanted in the depression forming a highly doped tunneling region. A tunnel oxide layer is formed on the substrate surface fully covering the tunneling region. Next, the floating gate layer is formed on the tunnel oxide layer. The gate isolation layer and control gate layer are formed over the floating gate layer. Subsequently, the spaced source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact openings are formed. Electrical contacts and metallurgy lines with appropriate passivation are formed that connect the source, drain and gate elements to form an electrically erasable programmable read only memory device.

Method of making an electrically erasable programmable memory device

A silicon semiconductor device has buried conductor lines formed therein. A layer of gate oxide, conductive structures, and spacer structures adjacent to the conductive structures on the gate oxide layer are formed. The substrate has implanted dopant ions of a relatively low level of surface concentration in the semiconductor material below the remainder of the conductive structures. The substrate has implanted dopant ions of a relatively medium level of surface concentration in the semiconductor material below the spacer structures. The substrate has implanted dopant ions of a relatively high level of surface concentration in the semiconductor material below the remainder of the substrate. Thus leakage is reduced by the profile of surface concentration of dopant in the semiconductor material of the substrate.

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I Lan, Taiwan

Jyh-Kuang Lin