Via Technologies, Inc.

Jyh-Fong Lin

Hsin-Chieh Lin

Chun-Chieh Chen

Yi-Bin Hsieh

Ke-Yuan Chen

Kuo-Hsin Chen

Tai-Haur Kuo

Jiin Lai

Kuo-Ping Liu

Did-Min Shih

Yu-Wei Lin

Chu-Yu Hsiao

Chin-Chi Chang

Chih-Chang Chien

Ming-Yu Wu

Pei-Hsiu Huang

An electrostatic discharge protection device having a P-type substrate, a common N-well formed in the P-type substrate, a common N-doped region formed in the first common N-well, wherein the common N-doped region is electrically connected to a reference voltage node. The device further has a common P-doped region formed in the common N-well, wherein the common P-doped region surrounds the common N-doped region, the common P-doped region and the common N-well form a common diode, a plurality of peripheral N-wells formed in the P-type substrate and surrounding the common N-well, each of the peripheral N-wells comprising a P-type doped region and a N-type doped region, wherein the P-type doped region is electrically connected to one of a plurality of I/O terminals, and a circular P-doped region formed in the P-type substrate and disposed between the common N-well and the peripheral N-wells, and the circular P-doped region surrounding the common N-well.

Electrostatic discharge protection device

An electrostatic discharge protection device, having a P-type semiconductor substrate set as floating; a first N-well and a second N-well formed in the P-type substrate; a first P-doped region and a second P-doped region formed in the first N-well and the second N-well, respectively. The first N-well and the first P-doped region form a first diode, and the second N-well and the second P-doped region form a second diode. A first N-doped region and a second N-doped region formed in the first N-well and the second N-well respectively. A third P-doped region is formed in the P-type substrate, wherein the third P-doped region is disposed between the first N-well and the second N-well, and the third P-doped region is electrically connected to the first N-doped region and the second P-doped region.

A signal processing circuit for adjusting an input signal and generating a corresponding digital output signal in an optical disk driver is provided. The signal processing circuit includes an attenuator for receiving and attenuating the input signal and then generating an attenuated output signal; a gain controllable amplifier for receiving and amplifying the input signal and then generating an amplified output signal; a control unit providing a control signal and a select signal, the control signal is directed to the attenuator and the gain controllable amplifier for enabling/disabling the attenuator and the gain controllable amplifier and for controlling their gains such that one of the attenuator and gain controllable amplifier is enabled at a time; and a waveform adjuster circuit for adjusting the amplified/attenuated output signal delivered from the gain controllable amplifier or the attenuator so as to generate the digital signal related to the input signal.

Signal processing circuit for optical disc drivers and the related method

The present invention is directed to a device and method for generating a reference voltage. A reference voltage generator comprises a first circuit, a second circuit, and an external device. The first circuit generates a positive temperature coefficient voltage. the second circuit is coupled to the first circuit, biased with a substantially constant current, produces a negative temperature coefficient voltage, and combines the negative temperature coefficient voltage with the positive temperature coefficient voltage as a reference voltage. The external device is coupled to the second circuit, and yields the substantially constant current.

Reference voltage generator and method for generating a bias-insensitive reference voltage

A multimode communications system includes a first communications module, a transmission module, a switch and a second communications module. The first communication module has a frequency modulator for modulating a dividing ratio to adjust an oscillating signal and selectively enabling the oscillating signal to have its frequency change with a variety of contents of a first communications signal by modulating the dividing ratio according to the contents of the first communications signal on a modulating mode or enabling the oscillating signal to have its frequency constant by keeping the dividing ratio unchanged. The switch is to selectively transmit the oscillating signal either to the transmission module when the frequency modulator is operating on the modulating mode or to a receiving end when the frequency modulator is operating on the constant frequency mode.

Multi-mode and multi-band RF transceiver and related communications method

A signal compensation circuit and associated method dynamically compensate for signal baseline wandering in a transmission line. The compensation circuit has a detection circuit and a correction circuit. The detection circuit first compares a transmission signal with a reference level and generates a comparison result. The correction circuit then corrects the transmission signal according to the comparison result. The compensation circuit can adjust its compensation over time based on the quality of the transmission signal.

Circuit for compensating a degraded signal and associated method

A clock recovery circuit for generating an output signal that is synchronized with an input signal. The clock recovery circuit includes a charge pump, a first filter, an oscillator, a switch circuit, and a second filter. When the charge pump operates, the switch circuit will disconnect the first filter from the oscillator. Additionally, when the charge pump stops operating, the switch circuit will connect the first filter and the oscillator such that the oscillator adjusts a frequency or phase of the output signal according to the output voltage of the first filter.

Clock recovery circuit and related methods

A high-speed, low-noise charge pump for use in a phase-locked loop. The charge pump is constituted by first and second cascode current mirrors, as well as first and second switching transistors. The first cascode current mirror includes a first output mirror transistor and a first output cascode transistor. The first switching transistor is interposed between the first output mirror and the first output cascode transistors. During assertion of a first control signal, the first switching transistor is turned on so a first mirror current can flow through an output node. Likewise, the second cascode current mirror includes a second output mirror transistor and a second output cascode transistor. The second switching transistor is interposed between the second output mirror and the second output cascode transistors. During assertion of a second control signal, the second switching transistor is turned on so the second mirror current can flow through the output node.

High-speed low-noise charge pump

A frequency divider for dividing a frequency of a clock signal by an odd divisor includes a flip-flop chain for latching signals having a number of flip-flops equal to the divisor. The frequency divider also has an XOR gate having two input nodes and an output node, one input node being electrically connected to the clock signal, the other input node being electrically connected to an inverted output node of the last flip-flop, and the output node of the XOR gate being electrically connected to clock input nodes of the odd flip-flops in the flip-flop chain. The frequency divider further has an inverter, an input node of the inverter being electrically connected to the output node of the XOR gate, an output node of the inverter being electrically connected to clock input nodes of the even flip-flops in the flip-flop chain.

Frequency divider for RF transceiver

An analog-to-digital data converter converts an input signal to corresponding digital signals. The data converter includes two sets of comparison units arranged in an interlaced sense to alternatively analyze the input signal, generate digital signals corresponding to the result of comparing the input signal and reference signals. Each of the comparison units has a positive output and a negative output, and the digital signal is generated by the negative output and the positive output of the comparison units in a differential way. When the comparison units of one set are performing auto-zeroing, the comparison units of the other set perform the data conversion to generate corresponding digital signals.

Data converter with background auto-zeroing via active interpolation

A clock generating apparatus and method for generating clock signals of different frequency. The clock generating apparatus and method receives and divides a main clock signal to obtain a reference clock signal. Then, the reference clock signal and the first feedback clock signal are phase-locked to obtain the first clock signal. Moreover, the reference clock signal and the second feedback clock signal are phase-locked to obtain the second clock signal. The reset signal and the first clock signal are received by a divider. The divider then outputs the first feedback clock signal. Another divider receives the reset signal and the second clock signal and then outputs the second feedback clock signal.

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Taipei, Taiwan

Jyh-Fong Lin