Lattice Semiconductor Corporation

Jye-Yuh Lee

Om P Agrawal

Bai Yen Nguyen

Brad Sharpe-Geisler

A programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide distributed random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks. Configuration memory cells store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, and the routing structure. In one embodiment, there are at least twice as many logic blocks in the first plurality of logic blocks than in the second plurality of logic blocks. In another embodiment, the first and second plurality of logic blocks are arranged in one or more rows, and the programmable logic device includes one or more rows of embedded block RAM.

Programmable logic devices with distributed memory

Systems and methods are disclosed herein in accordance with one or more embodiments of the present invention to provide programmable logic devices with non-volatile memory and a variable amount of distributed memory (e.g., in a cost-effective manner). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks. Configuration memory cells store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, and the routing structure, with at least one block of non-volatile memory to store configuration data that can be transferred to the configuration memory cells.

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San Jose, CA, United States of America

Jye-Yuh Lee