Taiwan Semiconductor Manufacturing Comp. Ltd.

Winbond Electronics Corporation

Jye-Yen Cheng

Dian-Hau Chen

Yu-Bey Wu

Chih-Hsiang Yao

Sheng-Hsuan Wei

Li-Yu Lee

Chun-Hung Chen

Chih-Ping Chao

Tai-Yang Wu

Chia-Tien Wu

Tai-Yen Peng

Hua-Chou Tseng

Yi-Chun Huang

TaiYang Wu

Harry-Hak-Lay Chuang

Chung-Long Chang

Jyh-Huei Chen

Kuo-Chiang Tsai

Chen-Hua Douglas Yu

Hua-Tai Lin

Chen-Nan Yeh

Shien-Yang Wu

Ken-Yu Chang

Alex Kalnitsky

Wen-Kai Wan

Chien-Chih Ho

Jeng-Shiun Ho

Wei-Chun Hua

Ming-Shuoh Liang

Chen-Yu Shyu

Pei-Ru Lee

Chia-Yi Su

Ming-Hsing Tsai

Wen-Chuan Chiang

Jian-Hong Lin

Minghsing Tsai

Cheng-Cheng Kuo

Yih-Yuh Doong

Wei-Chang Kung

Tzu-Chun Lo

Cheng Cheng Kuo

Luke Lo

Wei-Chan Kung

Ying-Wen Huang

Ying-Jen Kao

Hua-Chao Tseng

Ching-Hsiang Hsu Charles

Sen-Shan Yang

Sheung-Hsuan Wei

Semiconductor structures and method for manufacturing the same are provided. The method includes forming a first conductive structure over a substrate and forming a second conductive structure through a dielectric layer over the first conductive structure. The method further includes partially removing the dielectric layer to reduce a thickness of the dielectric layer along a first direction and forming a third conductive structure over the second conductive structure. In addition, a first portion of the third conductive structure is within a projection area of the second conductive structure along the first direction, and a second portion of the third conductive structure is outside the projection area of the second conductive structure along the first direction, and a first bottom surface of the first portion is spaced apart from a second bottom surface of the second portion by a distance along the first direction.

Method for manufacturing semiconductor structure having raised via contacts

A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

Semiconductor device comprising air gaps having different configurations

A method of fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer over a semiconductor substrate and forming first and second via contacts in the first dielectric layer and extending below a bottom surface of the first dielectric layer. The method also includes etching back the first dielectric layer to expose upper portions of the first and second via contacts. The method further includes depositing an etch stop layer conformally on the upper portions of the first and second via contacts and on the first dielectric layer. In addition, the method includes depositing a second dielectric layer on the etch stop layer and forming first and second metal lines in the second dielectric layer to be electrically connected to the first via contact and the second via contact, respectively.

Methods of fabricating integrated circuit devices having raised via contacts

In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

Semiconductor device and manufacturing method thereof

An interconnect structure includes a damascene structure, an inter-metal dielectric (IMD), a dielectric block and a metal via. The inter-metal dielectric layer is over the damascene structure. The dielectric block is embedded in the IMD layer and has a different etch selectivity than the IMD layer. The metal via is in the IMD layer and through the dielectric block to electrically connect the damascene structure.

Interconnect structure and method of forming the same

In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate. A first set of recesses is formed in the first dielectric layer. A metal layer is formed in the first set of recesses. A set of metal wirings is formed from the metal layer in the first set of recesses. A second set of recesses is formed in the first dielectric layer. A second dielectric layer is formed over the set of metal wirings and in the second set of recesses. A third set of recesses is formed in the first dielectric layer and the second dielectric layer. A third dielectric layer is formed over the metal wirings and in the third set of recesses.

A method for forming a semiconductor device is provided. The method includes forming a first dielectric layer over a semiconductor substrate and forming a first conductive feature extending into the first dielectric layer. The first conductive feature has a planar top surface. The method also includes forming a second dielectric layer over the first conductive feature. The method further includes forming a hole in the second dielectric layer to expose the planar top surface of the first conductive feature. In addition, the method includes partially removing the first conductive feature from the planar top surface of the first conductive feature to form a curved surface of the first conductive feature. The method further includes forming a second conductive feature to fill the hole after the curved surface of the first conductive feature is formed.

Formation method of damascene structure

Methods of fabricating an integrated circuit device are provided. The integrated circuit device includes a transistor formed on a substrate. The transistor includes a source region, a drain region, and a gate structure between the source region and the drain region. The integrated circuit device also includes a first dielectric layer over the transistor and a first via contact partially in the first dielectric layer and electrically connected to the source region. The integrated circuit device further includes a second via contact partially in the first dielectric layer and electrically connected to the gate structure. In addition, the upper portion of the first via contact and the upper portion of the second via contact protrude from the first dielectric layer.

Integrated circuit devices having raised via contacts and methods of fabricating the same

A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.

Method and system of generating layout

Methods of fabricating an integrated circuit device are provided. The method includes depositing a dielectric layer and a first hard mask layer in sequence over a substrate. The method also includes forming a patterned second hard mask on the first hard mask layer, and forming a third hard mask portion in an opening of the patterned second hard mask. The method further includes removing the patterned second hard mask to leave the third hard mask portion on the first hard mask layer, and etching the first hard mask layer to form a patterned first hard mask. In addition, the method includes etching the dielectric layer by using the patterned first hard mask as an etching mask to form trenches in the dielectric layer, and filling the trenches with a conductive material to form conductive lines.

Methods of fabricating integrated circuit devices having reduced line end spaces

A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The semiconductor device also includes a first dielectric layer over the semiconductor substrate and surrounding the first conductive feature. The semiconductor device further includes a second conductive feature over the first conductive feature. A bottom surface of the second conductive feature is between a top surface of the first conductive feature and a bottom surface of the first conductive feature. In addition, the semiconductor device includes a second dielectric layer over the first dielectric layer and surrounding the second conductive feature. The semiconductor device also includes an etch stop layer between the first dielectric layer and the second dielectric layer. A top surface of the etch stop layer is between the top surface and the bottom surface of the first conductive feature.

Structure and formation method of damascene structure

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Taichung, Taiwan

Jye-Yen Cheng