United Microelectronics Corp.

United Semiconductor Corp.

Jy-Hwang Lin

Ching-Chun Huang

Jung-Ching Chen

Yueh-Feng Ho

Rong-Ching Chen

Ming-Shing Chen

Ching-Hsing Hsieh

Wen-Chieh Wang

Chia-Chieh Yu

Shu-Jen Chen

Pei-Jen Wang

Sheng-Hsiung Yang

Tien-Shang Kuo

Tsan-Wen Liu

Rong-ching Chen

Hua-Wei Peng

Kuen-Syh Tseng

Fu-Hsuan Chu

Jim Su

Ming-Hsien Huang

A semiconductor structure includes a substrate, a plurality of image sensing devices formed in the substrate, at least a passivation layer formed on the substrate, a plurality of first metal patterns formed on the passivation layer, a plurality of gaps formed between the first metal patterns, an insulating layer lining the gaps, and a plurality of light-guiding structures respectively formed in the gaps. The light-guiding structures respectively include an anchor portion and a body portion, and bottom surfaces of the anchor portions being lower than top surfaces of the first metal patterns.

Semiconductor structure

First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as &#x2212;6V&#x2dc;12V, &#x2212;12V&#x2dc;6V, &#x2212;9V&#x2dc;9V etc.

Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage

A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of the channel stop doping regions. In addition, the grade drive-in process used to activate the grade doping regions in the high-voltage device area and the gate oxide growth of the high-voltage devices are performed simultaneously.

Method for fabricating integrated circuits having both high voltage and low voltage devices

The present invention provides a method of forming devices having different operation voltages. First, a substrate having an HV region, an MV region, and an LV region is provided. Then, at least a deep well encompassing the LV region and the MV region is formed in the substrate. Afterward, a plurality of n-wells and a plurality of p-wells are in the HV region, the MV region, and the LV region. Following that, a plurality of HV devices are formed in the HV region, a plurality of MV devices are formed in the MV region, and a plurality of LV devices are formed in the LV region.

Method of forming devices having three different operation voltages

The present invention provides a method of integrating at least one high voltage metal oxide semiconductor device and at least one Submicron metal oxide semiconductor device on a substrate. The method comprises: providing the substrate, forming a plurality of shallow trenches having different depths on a surface of the substrate, and forming a plurality of silicon oxide layers filling up the shallow trenches, and a top of each of the silicon oxide layers being in the shape of a mushroom.

Method of integrating high voltage metal oxide semiconductor devices and submicron metal oxide semiconductor devices

A multi-film capping layer having a cobalt layer, a barrier layer, and a stuffing layer is disclosed, wherein the barrier layer isolates the cobalt layer from the stuffing layer. The multi-film capping layer is formed on a gate transistor and applicable to a self-aligned silicide (salicide) process, so that a sheet resistance of the salicide layer on conductive regions of the gate transistor is significantly reduced. The stuffing layer further prevents entry of oxygen or moisture to the salicide layer, thus no cobalt oxide is formed when RTP is performed. Without formation of the cobalt oxide, the salicide process is free from the bridging issue and the filament issue.

Multi-film capping layer for a salicide process

A method of fabricating an interconnect is described in which a conductive layer, an anti-reflection layer and a cover layer are sequentially formed on the substrate to form a conductive plug with its bottom situated in the anti-reflection layer. The cover layer and a portion of the anti-reflection layer and the conductive layer are remove to form an opening exposing the substrate and to define the conductive lining structures. A conformal polysilicon oxide layer is formed on the substrate and a first dielectric layer is also formed, filling the opening. A conformal isolation layer is then formed on the substrate, followed by forming a second dielectric layer covering the entire substrate. A planarization procedure is further conducted to expose the conductive plug.

Fabrication method of an interconnect

An architecture of poly fuses includes a number of fuses, a dielectric layer, a sheet-like etching stop layer, and a passivation layer, wherein the sheet-like etching stop layer further includes a number of slices, and wherein each of the slices corresponds to one of the fuses underneath. The architecture of poly fuses according to the invention reduces the energy dispersion during the defective recovering process, and improves the recovery rate for defective memory cells.

Architecture of poly fuses

The invention provides a method of manufacturing a metal interconnect. A substrate having a metal line formed thereon is provided. An anti-reflection layer is formed on the metal line. A dielectric layer with a relatively low dielectric constant is formed over the substrate. A patterned photoresist layer is formed on the dielectric layer. The patterned photoresist layer has an opening exposing a portion of the dielectric layer. The portion of the dielectric layer exposed by the opening is removed to form a via hole. The patterned photoresist layer is removed by an O.sub.2 --H.sub.2 O--CF.sub.4 plasma. The pressure of the O.sub.2 --H.sub.2 O--CF.sub.4 plasma is about 800-1000 torr. A cleaning process is performed by a post-stripper rinse solution and de-ionized water without using an acetone solution. A barrier layer is formed over the substrate by chemical vapor deposition. A metal nucleation is performed for a long time by chemical vapor deposition to form metal nuclei on the barrier layer. A metal layer is formed to fill the via hole by chemical vapor deposition.

Method of manufacturing interconnect

An improved method of fabricating an unlanded via hole on a semiconductor substrate is provided. A conductive line and a patterned anti-reflection coating layer are sequentially formed on the substrate wherein the patterned anti-reflection coating layer has a smaller width than the conductive line and a portion of the conductive layer is exposed by the patterned anti-reflection coating layer. A planarized dielectric layer is formed over the substrate to cover the patterned anti-reflection coating layer and the conductive line. A via hole is formed in the planarized dielectric layer to expose portions of surface and sidewalls of the patterned anti-reflection coating layer as well as the conductive line.

Growing community of inventors

Hsin-Chu, Taiwan

Jy-Hwang Lin