Texas Instruments Corporation

Jy-Der Tai

Edison H Chiu

Morris D Ward

Kenneth L Williams

Te-Chuan Hsu

Quang-Dieu An

George J Ehni

Thomas A Carroll

A method and circuitry are provided for modularized single transition counting. A count signal is provided on a count line (436). A single transition count is modified in response to the count signal. The single transition count has a plurality of bits (418, 416) provided by at least one first module (404) and at least one second module (406). The first (404) and second (406) modules are alternately coupled in series to an input module (402) so that one (404) of the first and second modules has an input (460a, 466a) coupled to an output (420, 468) of the input module (402) and so that each additional one (406) of the first and second modules has an input (482a, 488a) coupled to an output (472a, 478a) of an associated one (404) of the second and first modules, respectively.

Circuitry and method for modularized single transition counting

A sequential memory (10) includes synchronous write control circuitry (26) and synchronous read control circuitry (22). The synchronous write control circuitry produces an Input Ready (IR) signal synchronous with the WRTCLK signal. The synchronous read control circuitry (22) generates a Output Ready (OR) signal synchronously with the RDCLK signal. A RSAM (read sense amplifier) signal is provided to read the sense amplifier associated with a memory (12) responsive to the RDCLK if a RAMRDY signal indicates that a read from this location may be requested on the next clock cycle.

First-in first-out memory

A sequential memory (10) uses interleaved memories (12a-b) with associated output buffers (22a-b) accomplish high data rates. Data access control circuitry (18) and bank select circuitry (20) control the order in which the memory banks (12a-b) are written to and read from. Output buffer circuits (22a-b) allow a data word to be read instantaneously after it is written to the sequential memory (10).

Sequential memory

A data access controller (10) is comprised of a control circuit (12) and an output data latch (14). The control circuit (12) receives a READ and WRITE signal (30,32) and produces a plurality of control signals (22). The output data latch (14) allows either incoming data (24) or data from a memory (16) to be propagated to the output for data access depending on the state of the control signals. The data access controller (10) enables faster data access of first in, first out memory structures.

Data access controller and method

In a method and circuitry for variable single transition counting, a count signal (178) is provided on a count line. A direction control bit (264) is output on a direction control line. A significant bit (278e) is output on a significant bit line. A first single transition count (278a-d) is incremented in response to the count signal (178) and to the direction control bit (264) having an incrementing logic state. The first single transition count (278a-d) is decremented in response to the count signal (178) and to the direction control bit (264) having a decrementing logic state. The first single transition count (278a-d) and the significant bit (278e) together form a second single transition count (278a-e). The second single transition count (278a-e) is compared against a preselected value (296), and a comparison signal (320) is output in response to the second single transition count (278a-e) being equal to the preselected value (296 ). The direction control bit (264) and the significant bit (278e) are toggled in response to the comparison signal (320), such that a value of the second single transition count (278a-e) may be changed in response to the preselected value (296).

Circuitry and method for variable single transition counting

A look-ahead flag generator generates a flag signal corresponding to the occurrence of a predetermined value stored in a counter (10). The output of the counter outputs any of a plurality of values, the values including the predetermined value and at least one boundary value that is one unit of increment or decrement displaced from the predetermined value. A clock signal source (13) is coupled to a first input of the counter (10) to indicate a decrement or an increment to the value stored in the counter (10). An up/down signal source (11) is coupled to a second input of the counter to indicate whether an increment or a decrement of the stored value should be performed. Predetermined states of the up/down signal and the clock signal are operable to cause a boundary value stored in the counter (10) to be changed to the predetermined value. A predecoder (12) is coupled to an output of counter (10) for decoding the boundary value. A latch (132) stores the decoded boundary value. A gate circuit (111, 117, 139) is coupled to the latch (132), a flag signal output, the up/down signal source (11) and the clock signal source (13) and is operable to generate the flag signal in response to the stored decoded boundary value and the predetermined states of the up/down signal and the clock signal.

Look-ahead flag generator

An arbiter (52) is operable to supply an up/down signal (11) and a clock signal (13) to an up/down counter (10) so that the up/down counter (10) can count the difference between read requests (54) and write requests (56) experienced by an associated FIFO memory. The arbiter (52) is operable to receive asynchronous read and write requests (54, 56) that are closely spaced in time or appear simultaneously, and to store the read request in a read latch (104) and the write request in a write latch (92). A decision circuit (62) is operable to determine priority between the read and write requests, and processes the request that is awarded priority. Once the first priority request has been processed, the stored non-priority request is then processed.

Method for assigning priority to read and write requests received

A solid state memory system is arranged in a plurality of blocks of memory cells, the memory cells in each block arranged in columns and rows. When the memory system is addressed for a memory reference, block selection circuitry selects one block of the plurality of blocks, excluding all of the other blocks. Each block has a set of sense amplifiers, corresponding in number to the number of bits in the output word. Each sense amplifier is connected to an isolation switch. The outputs from the sense amplifiers connected to the non-selected blocks are thereby isolated from the sense amplifier outputs from the selected block to minimize loading of the sense amplifier outputs from the selected block. The memory cells in each block are interconnected by metal row conductors and by metal column conductors.

Architecture for memory multiplexing

An arbiter (52) is operable to supply an up/down signal (11) and a clock signal (13) to an up/down counter (10) so that the up/down counter (10) can count the difference between read requests (54) and write requests (56) experienced by an associated FIFO memory. The arbiter (52) is operable to receive asynchronous read and write requests (54, 56) that are closely spaced in time or appear simultaneously, and to store the read request in a read latch (104) and the write request in a write latch (92). A decision circuit (62) is operable to determine priority between the read and write requests, and processes the request that is awarded priority. Once the first priority request has been processed, the stored second non-priority request is then processed.

Fast real-time arbiter

A CMOS output pair provides rapid switching speed while avoiding excessive noise levels developed across the power supply parasitic inductance. Both the P-channel and N-channel transistors of the output pair actually comprise a plurality of sub-transistors with their source to drain current paths connected in parallel. As a result of novel RC coupling of a switching signal from gate to gate of either of the plurality of sub-transistors, the sub-transistors are caused to turn on sequentially. Since none of the sub-transistors is capable of supporting the current that must be carried by the totality of sub-transistors making up either the P-channel or N-channel transistor, the increments of current as each sub-transistor turns on are small relative to the total.

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Jy-Der Tai