Freescale Semiconductor,inc.

Stmicroelectronics S.r.l.

Stmicroelectronics Gmbh

Nxp Usa, Inc.

Juxiang Ren

Stefano Pietri

Chris C Dao

Anis Mahmoud Jarrar

Robert S Jones, Iii

Robert Scott Ruth

V Srinivasan

Douglas Alan Garrity

Mike Robert Garrard

Bernard J Pappert

Nicolas Grossier

Edward J Hathaway

Mark A Kearney

Jeff L Warner

Nicolas Grosssier

Jayme W Richard

An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.

Method for testing comparator and device therefor

A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal. In one example, the first voltage source supplies, via the diode, the substrate terminal of a first transistor of the plurality of transistors during a power-up, and the second voltage source supplies the substrate terminal of the first transistor after the power-up.

Substrate bias circuit and method for biasing a substrate

A system having a power on reset circuit including a voltage divide), a multiplexer coupled to two outputs of the voltage divider, a first comparator coupled to the multiplexer and a reference, a logic gate coupled to the first comparator, a second comparator coupled to one of the two outputs of the voltage divider, and an emulation gate coupled to the second comparator.

Devices and method for testing power-on reset voltage

A supply voltage regulation system for an IC including a temperature sensor that detects temperature of the IC, a scaling resistor coupled between a power grid and a feedback node of the IC, a regulator amplifier that compares a voltage of the feedback node with a reference voltage for developing a supply voltage for the IC, and a temperature scaling circuit that drives a scaling current to the scaling resistor via the feedback node to adjust the supply voltage based on temperature. The temperature scaling circuit may include one or more comparators that compare a temperature signal with corresponding temperature thresholds for selectively applying one or more bias currents to the scaling resistor. The scaling resistor may be coupled to a hot point of the power grid. A voltage difference between a hot point of a ground grid may be converted to a bias current applied to the scaling resistor.

Supply voltage regulation with temperature scaling

A voltage regulator includes an amplifier having a first input coupled to a first reference voltage and a second input coupled to a voltage feedback signal; a multiplexer having a first input coupled to an output of the amplifier, a second input coupled to a voltage clamp signal, and a control input; and a control circuit having a first input coupled to an over current indicator, a second input coupled to a no over voltage indicator, a third input coupled to a timer signal, and an output coupled to the control input of the multiplexer.

Voltage regulator with current limiter

An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.

Integrated circuits and methods for monitoring forward and reverse back biasing

A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

System and method for controlling bypass of a voltage regulator

A semiconductor device includes CMP dummy tiles () that are converted to active tiles by forming well regions () at a top surface of the dummy tiles, forming silicide () on top of the well regions, and forming a metal interconnect structure () in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.

Active tiling placement for improved latch-up immunity

A voltage regulator includes a transistor, a comparator, and a compensation circuit. The comparator has a first input terminal coupled to receive a clock signal, a second input terminal, and an output terminal coupled to a control electrode of the transistor. The compensation circuit has a first input terminal coupled to receive a reference voltage, a second input terminal coupled to the output terminal of the voltage regulator, and an output terminal coupled to the second input terminal of the comparator. The compensation circuit has a filter circuit. The filter circuit has a first RC time constant during startup of the voltage regulator, and the filter circuit has a second RC time constant during normal operation. Changing the RC time constant for startup prevents an overshoot of an output voltage of the voltage regulator.

Switched mode voltage regulator and method of operation

An analog to digital converter has an input circuit, a computation circuit, an initialization circuit, and an output circuit. The input circuit is for receiving an analog signal and has a pair of outputs. A computation circuit has a pair of inputs coupled to the pair of outputs. The computation circuit has an amplifier having a pair of complementary outputs (Outp, Outn). The initialization circuit is coupled to the complementary outputs and is for biasing the complementary outputs at a time prior to the computation circuit beginning a computation on the analog signal. The output circuit is coupled to the pair of complementary outputs and provides a digital signal.

Analog to digital converter with amplifier

An analog-to-digital converter (ADC) device includes an input terminal to receive an analog signal, an analog component, and control logic. The analog component includes an amplifier having an input and an output and a capacitor network coupled to the input and the output of the amplifier. The capacitor network comprises a plurality of capacitors. The control logic is configured to, in a first mode, configure the capacitor network and the amplifier in an amplification configuration to amplify the analog signal by a predetermined gain to generate an amplified analog signal. The control logic further is configured to, in a second mode, configure the capacitor network and the amplifier to generate a series of one or more residue voltages using the amplified analog signal.

Analog-to-digital converter with variable gain and method thereof

A circuit comprises a reference voltage generating circuit, a first switch, a second switch, and a capacitive element. The reference voltage generating circuit has an input and output terminal for providing a reference voltage. The first switch has a first terminal coupled to a first power supply voltage terminal, a second terminal coupled to the input terminal of the reference voltage generating circuit, and a control terminal for receiving a first control signal. The second switch has a first terminal coupled to the output terminal of the reference voltage generating circuit, a second terminal, and a control terminal for receiving a second control signal. The capacitive element has a first plate electrode coupled to the second terminal of the second switch, and a second plate electrode coupled to a second power supply voltage terminal.

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Austin, TX, United States of America

Juxiang Ren