Intel Corporation

Justin Tippetts

Pavan Kumar

Norma Bettine

Disclosed herein are systems and methods for self-isolation of power-management integrated circuits (PMICs) of memory modules under and in response to fault conditions. In an embodiment, a PMIC is operably engaged with a memory module that is operably engaged with a platform. The memory module includes a non-volatile-memory block having a power supply controlled by the PMIC. The PMIC has a critical-fault signal pin that can be asserted to shut down the platform. The PMIC determines whether at least one critical fault occurred during a prior cycle, and also determines whether a critical fault occurs during a bootup sequence during a current cycle. Based on determining that a prior-cycle critical fault occurred and that a critical fault occurs during the bootup sequence, the PMIC sets a critical-fault indicator corresponding to the current critical fault; powers down the power supply; and does not assert the critical-fault signal pin.

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Hillsboro, OR, United States of America

Justin Tippetts